32.768 tolerance on TWL6032

All crystals have small electrodes that connect the crystal to the package pins. The electrodes form a shunt/holder  capacitance in parallel with the crystal's LC model.Typical values range from 1pF to 6pF. Some oscillators will not tolerate excessive holder capacitance. This is particularly true at higher frequencies as the reactance of the holder capacitance decreases. Make sure the crystal vendor's holder capacitance is within the allowable range for your oscillator. As a general rule, minimize the holder capacitance (the smaller, the better).

Internal cap which are placed in parallel to the external cap and combination of all will provide the total Cl. this is 0 in bacup bmode because device disconnectes them internally in back mode to save power.

The device has a way to compensated 1s / hour of an off set using the software. you can use that as explained in datasheet under 32K clk section of chapter 4 to achieve the performace you care looking at.

The crystal we have now is a mature product in a surface mount package so it is already in a holder inside the package and the manufacturer has constructed the device within its specs.  For that device the vendor has stated that the total external capacitance (including the 2x parallel load capacitors, the chip input capacitance, and the PCB parasitic capacitance) must present a parallel load capacitance of 12.5 pF total to the crystal to meet the crystal freq tolerance of +/- 20 ppm.

We wish to confirm the external capacitor values (Cx1 and Cx2) to meet the crystal vendor requirement of 12.5 pF.  We use the following formula to calculate this - please advise if incorrect:

Cl = (Cx1+Cx2)/(Cx1*Cx2) + Cparasitic + Cin

Cl = 12.5 pF (crystal vendor requirement)

Cx1, Cx2 = external discrete capacitors

Cparasitic = 2 pF (assumed PCB trace capacitance per trace)

Cin = ?? (PMIC input capacitance between OSC32KIN and OSC32Kout)

Can you please re confirm that the internal capacitance spec of 8 - 12 pF is the input capacitance of each of the OSC32KIN and OSC32KOUT pins.  If we use 10 pF for this figure in our calculation, the external capacitors Cx1 and Cx2 calculate out to be 13 pF  This is consistent with the PMIC spec of 15 pF per capacitor including PCB parasitics of 2 pF.

We are using 13 pF capacitors, but the crystal frequency is too low.  Something is incorrect. Please advise.  Is 2 pF too much or too little for typical parasitics?

Please also let us know the answer to the qu....what does Cshunt spec of 1.4 pF mean?

Please refer to my explaination above for Chunt, this is a spec parameter for crystal.

Also we have an EVM on which we are using 12.5 pf http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=swcu105&fileType=pdf.

so 12.5 pf should be fine, how slow is your clk ?

Our clock is slow by about 20 ppm on aveage, so instead of +/- 20 ppm we are getting about +0/-40 ppm.  We don't have a large test sample to confirm distribution yet.

In the EVM the parallel load cap used is 12 pF.  We are using 13 pF.  That might be the value we need to use.

I still don't see where you explain what Cshunt is.  Please clarify.  Do you mean the holder shunt capacitance of the crystal.

Yes i mean the holder shunt cap of crystal