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Peak Current Mode control in UCD3138

Tom Ki
Intellectual 265 points
Other Parts Discussed in Thread: UCD3138

Hi all

Currently, I am developing the simple code for Peak current mode control in UCD3138. However, I have experienced some problem in the development. Hopefully, TI people and some expert could give me some suggestion.


My code has been adaped from voltage mode control and the sample code from phase-shift full bridge converter(PWR027_PSFB_play_vin). According to the application notes of "UCD3138 Digital Power Peripherals
Programmer's Manual", I have set the corresponding and necessary registers stated as follows:

Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 0;    

Dpwm0Regs.DPWMCTRL0.bit.CLA_EN =0;

Dpwm0Regs.DPWMEV1.all = 0;             

Dpwm0Regs.DPWMEV2.all =(int)(PERIOD *.95);      

Dpwm0Regs.DPWMPRD.all = PERIOD;        

Dpwm0Regs.DPWMCTRL0.bit.BLANK_A_EN  = 1;

Dpwm0Regs.DPWMBLKABEG.all = 0;

Dpwm0Regs.DPWMBLKAEND.all = 500;                           

FeCtrl2Regs.EADCCTRL.bit.D2S_COMP_EN = 1; FeCtrl2Regs.EADCCTRL.bit.EADC_MODE = 5;     FeCtrl2Regs.EADCCTRL.bit.EADC_ENA = 1;              

FeCtrl2Regs.RAMPCTRL.bit.PCM_START_SEL = 0;     FeCtrl2Regs.EADCCTRL.bit.AFE_GAIN  = 3;            

FeCtrl2Regs.EADCDAC.bit.DAC_VALUE = 11000;   

      

FeCtrl2Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 500;

FeCtrl2Regs.RAMPCYCLE.bit.SWITCH_CYC_PER_STEP = 0;

FeCtrl2Regs.DACSTEP.bit.DAC_STEP = 43256;

FeCtrl2Regs.RAMPCTRL.bit.RAMP_EN   = 1;      

LoopMuxRegs.FECTRL2MUX.bit.DPWM0_A_TRIG_EN = 1;

LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL = 2;

LoopMuxRegs.APCMCTRL.bit.PCM_EN = 1;

LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL = 0;         

 

Dpwm0Regs.DPWMCTRL0.bit.CBC_PWM_AB_EN    = 1;   Dpwm0Regs.DPWMCTRL0.bit.CBC_ADV_CNT_EN = 1; Dpwm0Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN = 0;             

FaultMuxRegs.DPWM0CLIM.bit.ANALOG_PCM_EN = 1;

Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 1;    

 

It is supposed that the error signal from front end 2 will compare with the ramp signal in Front-end’s DAC register and then sent the cycle by cycle fault signal to the fault handler via fault mux(P.87). In that case, should I set or clear the value of the Dpwm0Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN?

If Dpwm0Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN is clear, however, the dpwm0A gives maximum duty cycle no matter I input the voltage in EAP2. If the bit  set, the dpwm0A gives zero duty cycle no matter what the input is.

 

Am I missing any important steps? Is it necessary to do the Peak current mode control under interrupt?

Best Regards

Tom