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how to understand the PH pin spec on TPS54622

jack zhu
Prodigy 20 points
Other Parts Discussed in Thread: TPS54622, TPS53313

Hi, I have a question about the PH pin voltage spec on the datasheet of TPS54622.

the absolute maximum ratings table shows that the PH pin voltage can  down to -1V, but when I put a voltage source on the PH pin, looks like it will be clamped at -0.56V and then current goes up. ( the internal body diode is on).

how the -1V spec is defined? and what kind methold that I can verify it?  thanks.

  • 0
    TI__Expert 4350 points

    Jack,

    The spec for the PH pin is exactly as you mention, it is simply an indication that the PH voltage will be clamped by the LFET body diode on the low end, and the HFET body diode on the high end. For a DC measurement, the PH voltage will be clamped by the forward voltage of the body diode.

    During operation, the PH pin voltage can temporarily exceed the DC voltage you measured. This is because the output inductor will normally be carrying current and will draw that current from one of the body diodes very quickly during the dead time. Due to parasitic inductances in series with the body diodes (both internally and externally), the measured voltage can temporarily exceed the 0.56V you measured. You would want to place the inductor pin as close to the PH pins as possible, and minimize the parasitic capacitance at the PH node so as to minimize the ringing and peak voltages seen at PH.

    Regards,

    MC.

  • 0 in reply to Martin Cardella
    Prodigy 20 points

    Hi Martin, thanks for your reply.

    I found that the SW rating of TPS53313 can down to -2V (DC). does it mean TPS53313 is more reliable than TPS54622 (-1V DC on PH)?  any special in the TPS53313 for the SW pin? I mean why it can down to -2V?

  • 0 in reply to jack zhu
    TI__Expert 4350 points

    Jack,

    The FETs in these two devices are not the same, so they won't have the same ratings. However, the latest datasheet for the TPS54622 has a 10nSec rating (-3V) and a 5nSec rating (-4V).

    If your concern is related to the actual voltage you will see during operation, there will not be much difference between the two devices. Of greater importance is designing a good layout such that parasitic elements are minimized. The voltage at the SW pin (or PH pin) will be clamped by the body diode of either FET. There is no situation where you would try to impose a voltage at the SW pin from some other external source.

    In order to design a good layout to avoid excessive spikes at SW, you will need to have the input cap bank (MLCCs) placed right up against the device power pins and on the same layer as the device, not connected through vias. The AC pin of the choke needs to be placed as close to the device as possible and also on the same side. The copper area at the SW node should be minimized and only big enough to cover the associated pins. Do not extend the SW node copper for heat sinking purposes because it adds undamped capacitance at the SW node and this capacitance will resonate with the parasitic inductance in the power path. The DC pin of the choke and the output cap bank should loop back toward the device power ground pins and not out toward the load. This will minimize the impedance of the output filter and reduce ripple and noise at the source. It is recommended to design a simple R-C snubber from SW to GND. This snubber will help to further reduce the spikes and ringing at the SW node.

    If you follow good layout practice, the peak voltage at the SW pin will not be an issue with either device.

    Regards,

    MC.