Hello e2e,
My customer has a question for you about the layout you provided:
There is no wall between analog and digital on the silicon however, so my first intuitive thought would be wrong. They bring out the ground to separate pins because there’s inductance in the bond wires. So my thought is to connect them together with a fat trace right at the part. Maybe that’s not right, though, because the via has some inductance, similar to the bond wires although maybe not as bad. By this reckoning, I should have separate vias going to the same copper plane.
I’m trying to do this on two layers, so ground might be fat traces on the back. Is two-layers not recommended for this part?
Thank you,
Natallia