Just finishing a re-layout of a TPS51116PWP design for DDR3.
The datasheet's Layout Considerations advice seems to conflict with the layout of the evaluation board TPS51116EVM.
Two questions. Any advice would be greatly appreciated, thank you.
1) When using the external current sense resistor with the PWP chip, should the RC snubber connect from LL directly to PGND (as per datasheet Layout Considerations, i.e. across FET+current sense resistor), or to CS (as per EVM layout, i.e. directly across the FET).
2) Our current sense resistor is about 12mm from the TPS51116 pins 15 (CS) and 16 (PGND). How should we join the PGND pin to PGND at the current sense resistor ? .....
a) Use a wide trace from pin 16 directly to the current sense resistor (e.g. 25mil as per datasheet) before it connects to the inner ground plane, or
b) Connect pin 16 directly to an inner ground plane (as per EVM).
The current sense resistor is already tied to the inner ground plane with several vias. I believe the PGND pin is used for the FET gate return, so the trace in option a) above would be carrying this current.