• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 64 subscribers
  • Views 3520 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ34Z100 I2C spike on SDA line

ravindra kumar
Prodigy 10 points

Hi 

I am frequently getting spike/glitch on data line.

In the picture mentioned below, I have marked the spike with red

I have also encountered data transition when the clock is low after 9th clock, which i suppose is because the master lets the data line float for the slave to acknowledge.

Any theories on what might cause that sort of spike?

I2C Settings:

SCL - 100KHz

Pull up at SDA and SCL line 4.7Kohm

  • 0
    Intellectual 300 points

    You have pullup resistors on the line, and you will have brief moments when neither the I2C bus master nor the I2C bus slave device are driving the SDA line. During those "undriven" moments, the SDA line should return high.

    Without knowing any better, I think the glitches in your capture happened when (1) the I2C bus master released the data bus a little before the I2C slave device asserted ACK, and (2) when the I2C slave device released ACK a little before the I2C master started driving the SDA line again.