LP39798 enable

Q1) R1 ~ 49.9 ohm and R2 = 14k ... issues with 1.2V out.

A1) The 49.9 ohms for R1 will raise Vout about 4mV (≈0.3%) higher than Vfb. If a 4mV offset above Vfb is OK with you, then there is no issue. Otherwise, use zero ohms for R1.

Q2) Enable logic needs to be low at start up and only enabled by a FPGA 3.3V LVCMOS output later.

A2) Since the internal pull-up current on EN pin is so low (3uA), simply use a high value resistor from EN pin to GND to hold the device off. I suggest 200k ohms to 250k ohms. LVCMOS high output ~should~ be able to provide adequate current to pull the EN pin, along with the pull-down resistor, well above 1.34V to enable the device.

Hi Donald,

Thanks for your reply. So, a sample circuit as shown should work fine with a LVCMOS33 output enable from an FPGA? Please confirm.

Regards

Gaurav

Without knowing the specific DC voltage vs current characteristics of your 'FPGA OUT' pin, it's difficult to give an absolute determination.

Best I can offer is : This will ~probably~ work OK.

I would suggest eliminating the 100k resistor, unless you know something about the 'FPGA OUT' behavior that would suggest that it is needed.

That sounds adequate.

I would still remove the 100k, or make it a much smaller value. Say ... no more than 1k.