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LMZ30602 output capacitors

Robert Curtis
Intellectual 430 points
Other Parts Discussed in Thread: LMZ30602

Hello,

I am using Webench to construct a power conversion circuit with the LMZ30602.  I have a couple of questions with regard to the input and output capacitors.

I will have three LMZ30602 regulators producing 1v, 1.8v, and 3.3v.  Webench lists maximum values for the input capacitance (300uf).  If all three devices are using the same source power, should I have any concerns with having too much input capacitance?

Also, for the output capacitance, I would like to use a C1206C475K3RAC 47uF capacitor for Cout1 instead of the offerings in Webench. Is this acceptable?

Also, the regulators will be powering an Artix 7 which requires considerable decoupling.  Should there be consideration given with regard to the FPGA decoupling when determining the correct output capacitors Cout1 and Cout?

Thanks for the help,

Rob Curtis

  • 0
    TI__Mastermind 23845 points

    Hi Rob,

    There is no issue with having too much input capacitor. The only problem that i can see is that the upstream supply might hit a current limit because of the inrush current going to the input capacitor of LMZ30602.

    Just make sure you have a good decoupling capacitor (close to the IC VIN pin) for the LMZ30602 and also make sure that the IRMS current rating for the capacitor is not exceeded. 

    As for your output capacitor, what part number does the webench recommend? I look at your C1206C475K3RAC and it seems like a good capacitor (25V rated, X7R) to use. 

    I would say you can design the LMZ30602 output capacitor independent of what is the FPGA requires for decoupling. In this case you will need a Cout1 (ceramic capacitor) which is your 47uF and one bulk capacitor Cout2 of either 100uF or 330uF at the output of your modules.

    Thanks

    -Arief

  • 0 in reply to Arief Hernadi
    TI__Mastermind 23845 points

    Rob,

    A quick revision on the answer that i gave you earlier regarding the output capacitor. 

    If the location of the module is close to FPGA and there is no ferrite bead in between, then yes you can use the decoupling as part of the output capacitor of the module. 

    On the other hand if the location of the modules are far from the FPGA or if there is a ferrite bead before going to the FPGA rail, then you design the output capacitors independently. 

    Also if you have a ferrite bead, the feedback for the module should be taken before the ferrite bead. 

    Thanks

    -Arief