TPS51116 - Heating up in light load conditions

Andre Micallef

Other Parts Discussed in Thread: TPS51116

Hi,

I have recently designed anew board incorporating the TPS51116 to power two DDR3 SODIMM's. I have based my design on one of the reference designs shown in the datasheet. The implementation was designed for the following;

DDR3 Operation (1.5V VDDQ and VTT of 0.75)
RDSon Sense
Internal LDOin
Non-tracking discharge
DCAP operation

However during testing the package is heating up considerably (the surrounding components remain relatively cool) . Moreover I probed the DRVL (blue) and DRVH (orange) signals to see whats happening. It's evident in the first image that the frequency is much higher (and irregular) than the EVM board (the second image). Please note that both designs have no loads attached to them.

All components are similar to the ones used in the EVM and placed according to the suggestions listed in the datasheet. Is there anything I might have overlooked ? Moreover is there anything that might affect frequency generation apart from current sensing ?

Any help is much appreciated.

Regards,
Andre

over 11 years ago

0 JohnTucker over 11 years ago

TI__Guru**** 191445 points

TPS51116 has pulse skipping at light load. The actual load will determine the operating frequency. Once you reach CCM operation the frequency should stabilize. Can you post your schematic and layout?

0 Andre Micallef over 11 years ago in reply to JohnTucker

Prodigy 80 points

Thanks for your quick reply. Might I also add that the VDDQ is closer to 1.6V than the 1.5V originally designed.

Please find the schematic as pdf.
I also attached both the component placement and the top layer polygon layout for ease of viewing.

7485.TPS51116 - Schematic.pdf

Hope the above information helps.

Regards,
Andre

0 Andre Micallef over 11 years ago in reply to Andre Micallef

Prodigy 80 points

A few weeks has passed since my last post. Are there any updates regarding this issue?
Any help would be appreciated.

Regards,

Andre

0 JohnTucker over 11 years ago in reply to Andre Micallef

TI__Guru**** 191445 points

how much internal ground plane is attached to the thermal pad?

0 Andre Micallef over 11 years ago in reply to JohnTucker

Prodigy 80 points

Shouldn't the Thermal pad be isolated from PGND ? If I remember well there's only one via connected to the ground plane. Could this be the problem (due to a reduced return loop) ?

Thanks for all your help.

0 JohnTucker over 11 years ago in reply to Andre Micallef

TI__Guru**** 191445 points

The thermal pad should be well connected to internal PGND plane. The EVM uses 7 vias, 3 in the exposed pad area and 4 more directly adjacent to the IC.

0 Andre Micallef over 11 years ago in reply to JohnTucker

Prodigy 80 points

Thanks for your quick reply. All outer pads are connected through vias, however the thermal pad is not connected well enough when compared to the EVM (which could possibly the source of my problem) .

This is a bit confusing since the TPS51116 datasheet specifically states that the thermal land underneath the IC should not be connected to PGND.

Is there something else I might be missing regarding this issue?

Regards,
Andre

0 JohnTucker over 11 years ago in reply to Andre Micallef

TI__Guru**** 191445 points

If I read the datasheet correctly, it says not to connect the PGND pin to the exposed area under the IC. It should still be electrically connected.

0 Andre Micallef over 11 years ago in reply to JohnTucker

Prodigy 80 points

It could have been a misunderstanding from my part then.
Will correct the design and will post any future updates.

Thanks for all your help.

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TPS51116 - Heating up in light load conditions