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Atomic instruction

Gerhard Kreuzer
Expert 2600 points
Other Parts Discussed in Thread: UCD3138

Hi,

is an assignment to an int variable an atomic instruction at UCD3138? Cause there were two instruction sets, and the system 'mostly runs in thumb mode'-whatever this means, is  this an atomic instraction or 'mostly' an atomic instruction?

I have to bring up a save data exchange method between my background (program running in IRQ Service Routine) and foreground, code running in the for(;;) loop.

Thanks for helping.

With best regards

Gerhard

  • 0
    TI__Genius 17090 points

    Gerhard,

    An assignment to an int variable is not atomic.  There are two steps, regardless of whether the processor mode is ARM or Thumb.

    1.  Load register with value
    2. Write register into variable

    If an interrupt occurs between step 1 and step 2 which writes to the same variable, you will have a broken write – the write by the interrupt will be wiped out. 

    This is because the ARM is a RISC architecture – everything has to go through a register.  

    I think that some assignments can be non-atomic even in processors with read-modify-write architectures as well. 

    Happy Debugging,

    Ian Bower

  • 0 in reply to Ian Bower
    Expert 2600 points

    ... bad News.

    Ok, is there a simple way to disable/enable Interrupts to protect this Operation?

    Never used a UCD3138 before, so have to learn a lot, but documentation is ...

    With best regards

    Gerhard

  • 0 in reply to Gerhard Kreuzer
    TI__Genius 17090 points

    Gerhard, for this kind of stuff, I would suggest getting a copy of the ARM Architecture Reference Manual.  Our documentation doesn't cover the details of the ARM. 

    Our recommended approach to interrupts is to use the standard interrupt for scheduled events from 1 timer, and to use the fast interrupt for faults only. 

    We work pretty hard to minimize the conflicts between the background and the interrupts.  It's a small, cost sensitive embedded processor, not a PC.

    To disable the interrupts, you have to be either in ARM or privileged mode. 

    In privileged mode, you can write to the REQMASK register and zero everything out to disable interrupts.  Then to reenable, you can write ones to the desired locations in the same register.

    In ARM mode, you can write to the CPSR (current program status register) and modify the interrupt and fast interrupt disable bits. 

    We provide access to both of these hooks via the software interrupt.  If you look at the software interrupt code, you will find examples.  Although the software interrupt writes to the SPSR - saved processor status register.  That way it takes effect when the software interrupt returns. 

    If you look at the init_timer or init_timer_interrupt function, you will see some calls to these software interrupt functions.

    Happy Debugging,

    Ian Bower