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TPS54320 CLK mode to RT mode

tateo yamashiro
Guru 10890 points
Other Parts Discussed in Thread: TPS54320, TPS54160

Hi

My customer has a question about TPS54320.
Could you tell me about question.

[Question]
 My customer want to change CLK mode to RT mode.
 But the internal switching frequency drop to 100kHz first before returning to the switching frequency set by RT resistor.

  - If my customer agree this behavior, can they change CLK mode to RT mode?

  - How is the condition will it returning to the switching frequency set by RT resistor from 100kHz.

Best regards,

tateo

  • 0
    TI__Guru**** 191445 points

    Yes you are correct about that.  When the clock is removed, the PLL loses synchronization and the Fsw drops. The 0.5 V is ree-applied to the RT pin and the current thru the resistor restores the original RT set frequency.  It typically takes a few cycles to restore.

  • 0 in reply to JohnTucker
    TI__Expert 5305 points
    My customer is asking similar questions:

    -- QUESTION 1 --

    "The datasheet mentions that it's not recommended to switch from CLK mode to RT mode. It only mentions that the switching frequency drops to 100 kHz. How long is this transient? Is the output voltage still regulated in this condition? In this application there is a linear regulator, so the design can tolerate increased ripple voltage that results from the lower switching frequency."

    -- QUESTION 2 --

    "Finally, the recommended method to operate in both modes is to use a tri-state buffer. Most anything that is connected to the pin will have leakage, which I expect will change the RT frequency set point. Is there a way to estimate the frequency change per leakage current added? Also, the tri-state pin will add capacitance to the net. Is this pin susceptible to capacitance being added in RT mode? I'm thinking I could AC couple the CLK signal to minimize leakage current but would add capacitance."
  • 0 in reply to Brian Antheunisse
    TI__Guru**** 191445 points
    The clock input is a PLL for external clock and a current mirror with fixed voltage on RT pin for RT set frequency. With a set voltage on RT the RT pin current is proportional to the RT resistor value. The switching frequency in turn is set by the RT pin current . When the clock signal is removed it takes a finite time for the voltage at RT to settle back to its fixed point. During this time the switching frequency can drop very low. It is usually about 100 kHz, and usually recovers within 100 usec or so. I do not believe these values are characterized or tested. The output voltage will attempt to regulate. The issue is that the on and off times are quite a bit longer than you probably designed for. The p-p inductor currents can get quite large, possibly triggering OCP with the resultant loss of regulation.

    If you are only connecting one clock to one device, then you probably do not need to tri-state so long as the clock is present at start up and not removed during operation. If it is removed, the RT pin must be allowed to float to it's regulated voltage (0.5 V if I recall correctly). 5 V and 100 kohm reslts in 5 uA current for comparison.

    The abs max for the RT pin is -0.3 V. That technically precludes ac coupling, but I know for a fact that a lot of users do use ac coupling. What will happen is the internal ESD diode will clamp the negative excursion of the voltage to about a volt and the current is minimal compared to the rating of the ESD structure.
  • 0 in reply to JohnTucker
    TI__Expert 5305 points

    Thanks for the quick answer. Just for clarification:

    • So if we were to use the datasheet equation to try and account for leakage currents effect on Fsw, would the error in the equation and/or the .5V on the RT pin dominate the leakages?
    • There shouldn't be a problem adding capacitance to the RT pin?

    Thanks,

    Brian

  • 0 in reply to Brian Antheunisse
    TI__Guru**** 191445 points

    The datasheet equation is just curve fit from measured data.  It is not actually a design equation that you can modify to account for leakage current.

    You want to be careful about capacitance directly on that pin.  It may upset the regulation of the internal voltage source.  If you are planning to ac couple, you should probably look at the TPS54160 datasheet.  It has an example.  The circuit is optimized to be driven from a bench function generator, hence the 50 ohm termination.  You may want 1-2 kohm depending on your clock source.