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LM5088 excessive Vout ripple from SW node sub-harmonic oscillations at Vin=24V/5A for a 20V switcher

eric king
Prodigy 20 points
Other Parts Discussed in Thread: LM5088

To Eric Lee (Sang Yong Lee)

One more LM5088  issue (on about ½ of the boards built) exhibit SW node “sub-harmonic”  oscillation as TI calls it (causing 200mV Vout ripple)  when loading the 20V switcher with max load of 5A  at Vin_min = 24-25V (min. headroom) that results in 200mV of Vout ripple.

 

The Vramp requires slope compensation for Vout > 5V which is what we have  but with our new VCC ref. of 11.7V the Rramp calculation may be in question and especially the value of Vramp used for this calculation.

IOS = 20V x 5uA/V = 100uA

Vcc_typ = 7.8V

VRampNom, = 1.2V; VRampmax = 2.5V

For VrampNom : Rramp = 88K ;  For VrampMax : Rramp = 70.6 K

Use Rramp = 82.5 K

 

I have measured Vramp on one board and it is approx.. 250mV peak.  What value of Vramp is appropriate to use to  calculate Rramp for the added bias current ? ( No reference in the data sheet).

WE have been using Vramp = 1.2 – 2.5V but that seems too high  and now with our VCC = 11.7V  I need to adjust this and want to make sure we have the correct value.

I have sweep the Rramp from low to high resistance about the existing Rramp of 82.5K with no improvements.

 

A good board runs at D = 83% at Fsw = 215KHz with <50mV ripple and well spaces SW node cycles at Iload = 5A and Vin = 24V.  This indicates that we still have margin in the design for lower Vin at full load since Toff  is still approx. 750-800n at Fsw = 215KHz.

A board with the excessive Vout ripple => has varying SW pulse widths in repetitive sequences runs with D = 60% for a few cycles and then 93% for a few cycles and alternates. (see below waveform).

This only happens when the output is initially heavily loaded from no load or light load and Vin < 28V or so.  With no load or <1 A load the SW node cycles are well behaved at Vin =24V.

We need good operation from Vin = 24 – 38V and Iload = 0-5A

Here are my questions:

1)      What is causing this behavior ?

2)        Is it within the Vramp compensation ? 

3)      If so what can be done  to improve the Vramp compensation ?

4)      Will the loop compensation affect this to any degree  ?

5)      Are there any other parameters that may cause this behavior ?

 

I will try again to adjust the slope compensation and Cramp a bit but don’t want to waste time trying to compensate for IC process variation that I have not information about or is outside of any external adjustable compensation parameters.

Thanks

ERIC King (Carefusion) { eric.king@carefusion.com}