BQ76930 balancing issue

For the bq76930 and bq76940, allowed internal balance current is small, 5mA max.  The recommended Rc value is 1k nominal and max.  With a 4.4V cell this would give about 2.2 mA internal balancing.  The input and filter resistors Rf must be large to keep the supply voltage above Vshut during short circuit.

Cc would be selected for good filtering but must allow measurement during balancing.  Using the EVM value for Cc of 1 uF will allow observation of a voltage change when balancing, the more cells balanced, the larger the difference.  This is due to the filter settling time which is complex with the multiple-input multiple-element filter.  The parameter of interest is the tCB_RELAX, 12.5 ms.  You want to select Cc small enough to allow the filter to settle in the 12.5 ms with your algorithm.  Cells start measuring at the bottom of each group, so cell 1 and cell 6 should be the most significantly effected by the filter.  If balancing one cell at a time, you might not adjust the capacitor value much, if balancing multiple cells at a time you might move toward the 0.1 uF value.

The external balance can be p-ch like the EVM, or n-ch basically mirrored on each cell from the EVM circuit.  The FET selected should have a suitable Rdson at the voltage available (~ 1/2 the cell voltage when balancing starts) and be able to dissipate the required power.  The balancing resistor will set the current, it will need to be within reason, it will generate heat.  The zener diodes shown will typically be needed to protect the gate from transients during short circuit or large transients.  The gate resistor should be large again to avoid loading the filter caps during heavy load.  The common resistance at the cell group boundaries should be kept small since the cell groups balance independently, cell 5 can see a voltage change from cell 6's balanace current in the common resistance.  Typically this will mean carrying the trace for VC5's Rc as close to the cell as possible separate from VC5B's Rc (and similarly at VC10, VC10B for the bq76940). 

A 1V difference seems large, you may want to check your setup for a high impedance.  The cell groups balance at independent times, using a resistive cell simulator such as the EVM you will see the other group voltage rise due to balancing.  Use low impedance sources when checking balancing

Thank you for your answer.

I'm using an external balancing circuit, exactly like in the EVM. But, in order to obtain a proper behavior, I had to use following values:

• Rc very high (47k), in order to assure a proper p-MOS (BSS84) switching on
• Cc very small (I've removed it), in order to avoid slow transients (especially with the high Rc value) and to avoid any shift also on the near channel. In fact the 1uF value for Cc, also with Rc=1k, causes an increased voltage reading on the following channel that can be avoided only by reducing (or removing) such Cc. this effect seems to be evident also with a real battery pack.

Do you see any problem if I use a so high Rc?

By removing Cc, the only problem could be an increase of noise on readings?

Thank you again and best regards

Matteo

I'm designing a protection and balancing circuit for a 10S and 3P battery back, is it better to use an external balance with the BQ76930? if yes, what is the relation between the balancing time, the balance current and the Pack size [Ah]?

The internal cell balancing current is about 10mA and this adequate for most cells. You can add external cell balancing to support higher capacity packs to balance faster. Here is an app report on external cell balancing the helps to explain some of the parameters.

slua509.pdf

Internal cell balancing current is limited on the bq76930 as you indicate.  You might see section 4 of www.ti.com/lit/slua749 on balancing circuitry.  The input filter resistors will also affect the power during short circuit, see section 3.  1k input resistors are typical with the bq76930.  Size the external balancing resistor for the desired current considering the duty cycle.

Unfortunately balancing is not always simple and will depend on the cells, environment and usage of the system.

Consider the factors for imbalance in your system such as described in slua509, and any others which may be particular to your system.  Then consider how often the system will be charged.  Perhaps you determine the cell stack will imbalance by 1 mAh between charge cycles.  Since the TI gauge will typically balance during taper, determine the amount of time the system will remain in taper and how much time the gauge will use to balance.  If the imbalance leaves 1 cell high, that cell can balance down quickly.  If the imbalance leaves 1 cell low the others must be balanced down to match it, this will take longer as the gauge algorithm balances down the other cells within the limits of the AFE. 

So if your balance time during the taper is 1/2 hour and you have a 1mAh imbalance, the current to balance from a cell is would be 1mAh/0.5h or 2mA.  Since the AFE will duty cycle the balancing by 70%, the current needed in the circuit would be 2 mA/ 0.7 = 2.9 mA.  The bq76930 does not allow adjacent cells to be balanced, so the gauge would need to allow at least 2 alternating patterns for balance of all the cells but one, or half the balance time could be available for the cell pattern. Applying this duty cycle to the calculation would give a needed circuit current of  2.9 mA/0.5 = 5.8 mA.   If the algorithm in the gauge applies a different or additional duty cycle, that could be applied in the same way.  You may want to allow some margin in your calculation.

Since balancing will operate with fully charged cells during taper, your (external) balance resistor can be determined by (Cell charging voltage)/(Balance current).  If your FET on resistance is significant, be sure to include it when selecting your resistor.

If your user pulls the pack from the charger before taper and balancing are complete for that cycle, the pack would not be balanced in that cycle.  If the pack is cycled more rapidly than expected, the imbalance between charge cycles will be smaller and there will be less balancing to be done.  If the pack is cycled more slowly than expected, more imbalance may develop than can be balanced out in a single charge cycle. Note in the apnote or similar balancing apnotes that the effectiveness is typically shown by applying an imbalance and observing the convergence of capacity or voltage over time.  While the calculation above is in capacity, the CEDV gauges such as the one mentioned in the apnote above or used by the bq78350 gauge for the bq76930 will balance based on voltage measurement.  It is the change in voltage resulting from the change in capacity that the balancing algorithm can respond to.

Hopefully this analysis and calculation method is useful to help you determine an appropriate balance current and resistor.