Common Mode Choke on the output of TPS55010?

Hi Anthony,

Thank you for your thoughtful reply to my question. My application is measurement of a +/- 10V signal using a PGA280 and a microcontroller. The signal path is differential, so I don't know how important it will be to reduce the common mode noise. I don't have a feel for the range of magnitude of what the noise could be. I suppose in my case the loop area could be large since the analog voltage is generated off-board. My hesitation in using the Y-capacitor is that the data sheet discusses safety isolation and there being an upper limit of capacitance. I haven't seen any specs on the interwinding capacitance of the Wurth transformers referenced in the data sheet, so I don't know what that is. I'm not sure how to calculate a maximum capacitance that still maintains compliance with the UL standards. The common mode choke wouldn't affect the isolation rating, so it seemed like an easy approach.

I have done a little research on what drives interwinding capacitance, and it looks like the turns ratio of the transformer is the key contributor. And the relationship is proportional to the square of the turns ratio, so the +/- 15V reference design that uses an 8:1 transformer would have even more common mode noise associated with it than the 5V output version (2.5:1 transformer). I haven't seen interwinding capacitance specs on any of the Wurth transformers. The SN6501 circuit is supposedly quieter. Is that because the recommended transformers have lower turns ratios? Do you have any guidelines for determining the interwinding capacitance?

Best Regards,

Greg

The SN6501 will be quiter because of the different topology. With the TPS55010 using the Fly-buck topology, like a Fly-back topology, there is energy stored in the primary side of the transformer during the the on-time of the control switch and energy is transferred to the secondary output during the off-time. This results in the flow current flow switching during each switching cycle. The SN6501 uses a push-pull topology where the current flow through the transformer from primary to secondary is continuous. This is best for noise sensitive applications.

The interwinding capacitance of the transformer can typically be provided by the transformer vendor although they don't usually put this in their datasheets. I have the value for the 750331880 off-hand and it is 22 pF for example.

In regards to the UL standards I think if there is a limit to this capacitance to meet compliance it will be listed in the standard. There may be a maximum capacitance across the isolation barrier. I admit I have not read through the UL standards before so I will check with the person who originally wrote the statement to see if they have any more details. He's gone for the holidays so it may take about a week.

Hi Anthony,

Thank you very much for your reply from last year. I'm sorry it took so long to get back to you. I really appreciate the very informative comparison between the two technologies. My application is noise sensitive, so I am preferring the SN6501 solution. It would be nice if TI would develop a better version of the SN6501 that has current limiting in order to protect itself and the transformer. Or a linear regulator that has a settable current limit that was a companion product to the SN6501. TI makes eFuse's, but the cost is high for the low current levels involved. It seems like it could be a rather inexpensive product for low currents. A USB load switch might also work since they have current limiting features. I think I'd like the linear regulator with settable current limit the most, since I'd need a linear regulator anyway.

In the SN6501 data sheet there is an issue with the alternate topologies shown for generating higher voltages. The SN6501 requires full-wave rectification, otherwise there will be an imbalance in the currents of the two transistors of the SN6501, unless the load is symmetrical. I posted a question about it in the e2e forum and my suspicion was confirmed. Since I don't need a lot of +/- 15V current, I am planning to solve that problem with charge pumps from a 5V supply delivered by the SN6501 and transformer. Charge pumps are quiet, aren't they? The switching frequency is low, so I think the ripple rejection of most linear regulators should be able to filter it pretty well.

More often than not I work with digital circuits, so the TPS55010 is something I plan to use in the future. Would you please ask your colleague about the UL standards? It would be helpful to have a design ready to go when I need it.

Best regards,

Greg

Hi Greg,

I discussed this with him and the UL standards usually specify the leakage current through the isolation barrier. Generally speaking a larger Y-capacitance will increase the amount of leakage current because it will pass more AC current for a given change in voltage on either grounds. Y-capacitance becould be tuned while testing to the standards because in the final design there are other paths for the leakage current to travel such as through the transformer.

The Y-capacitance used on the EVM is a typical value that was selected based on other designs with a Y-capacitor.

Hope this helps.

Best Regards,
Anthony

Hi Anthony,

Thank you very much for discussing it with him. Yes, your answer helps. I can see now that the answer is not a simple one that can be answered without all of the specifics. When the time comes I am going to need to study up on the UL standards and analyze my particular circuit for leakage paths in order to determine the maximum capacitor that can be used. Maybe I won't need to worry about it as much if TI comes out with a higher-powered SN6501-like product that John Griffith of TI said you often have requests for.

Best Regards,

Greg