TPS54620 external synchronization clock requirement

Hello and thanks for the interest in TPS54620 -- 

A few notes/recommendations about using an external clock for TPS54620:

• You should still have a local RT resistor, even if using external synchronization.
• When synchronizing multiple TPS54620's to the same clock, it is recommended to buffer each clock separately. behind the RT pin is amplifier which tries to regulate the pin to 0.5V when no clock is present. If multiple RT pins are connected together, they will "fight" eachother. 
• Unless the clock is running, and clock transitions are coming continuously, pulling RT to ground, or up to the rail will cause the switching frequency to go to min/max respectively. 
• There is a minimum pulse width of ~20ns typical. There is no major duty cycle limitation, it should be OK anywhere from 5% to 95% duty cycle. 
• Current into the pin must be limited to 100uA absolute maximum. I would recommend adding a series resistance, especially if its going to be driven from a push-pull type I/O. 
• Switching will be synchronized to the falling edge of the clock.
• Synchronization is implemented via a phase-locked loop. Frequency/variation/jitter will probably just show up as a little extra switching jitter. Clock jitter is generally not an issue, because the frequency is relatively low, 200kHz-1MHz and ~20ns jitter is not uncommon for a switching regulator to begin with. Because synchronization is implemented via PLL, if the clock "disappears" during normal operation, there will be some time before the PLL detects it has lost "lock" and reverts to the internal oscillator. This may cause the output voltage to dip during the transition.