LM3409HV-Q1 Parasitic Capcitance on UVLO pin

Sakai: The parasitic capacitance of the LM3409 UVLO pin is between 5 -10pF.
David Zhang

Dear, David-san. 

Thank you for your valuable information. 

May I ask one more thing?

You are providing "LM3409 TINA-TI Transient Spice Model". 

I wonder the parameter was reflected to the model?

Best Regards, 

H. Sakai

Sakai san:
Sorry, I don't know if this parasitic capacitance is built into the Spice Model.
David Zhang

Dear, David-san. 

Thank you for your teachings. 

My customer would like to set the external resistors as below to reduce 

the part count and cost. 

Ruv1 = No placed (OPEN)

Ruv2 = Short to Vin

EN will be active by MCU after Vin become stable. 

I wonder it is no problem to use this device under such condition?

Best Regards, 

H. Sakai

Sakai san:

 

    Yes, the customer can disable the UVLO function by connnecting the UVLO pin directly to VIN.

 

David Zhang

Dear, David-san. 

Thank you for your reply. 

The minimum of Vin operating range is 6V. 

Is it no problem to disable UVLO function considering safety device operation?

Sorry, I would like to double-confirm. 

Best Regards, 

H. Sakai

Sakai san:
Disable UVLO won't affect the operation because the EN pin is high only when VIN is stable. The device will not operate at very low input voltage.
David Zhang

Dear, David-san.
I am feeling a mount of gratitude for all of your teachings.

What is the supply voltage source for internal Logic circuit?

I am very sorry to ask again and again, my customer is asking that and I can't
understand to check the internal block diagram.

Best Regards,m
H. Sakai