TPS27082 current

In alternative designs I see RS placed above Q2. On 27082L datasheet page 5 it is explained that RS<<R1 minimizes Q1's gate voltage, increasing Q1's VGS hence reduces RDSon. For this purpose RS can be either put above A2 or below.

For example, OnSemi AN places RS above Q2, so it is for most textbook examples.

Is there any particular reason 27082L places RS below Q2?

Ron,

Is there any formula for rush current?

Hui

Ron,

I also thought the note I referred to was not careful enough in choosing the signs.

Is there any difference putting RS (in the top post 27082l picture) below or above the Q2 MOSFET?


Hui

Ron,

We found rise time is good, just fall time too long.

Hui

Ron,

Thanks for answer.

I just experimented and replaced the output by a pure potentiometer with similar resistance. Whereas the rise time is several dozens of ns, fall time is more than 6 us.

In this configuration the load is purely resistive. Is there still anything we can do to to decrease fall time?


Additionally, if we replace C1 by a resistor, would it do any good to fall time AT ALL?


Hui

Ron,

This at least on the surface appears to be a change in the order (of magnitude, etc.). Could this in practice be a significant improvement? And why this is not listed in the manual?

Hui

Ron,

I am looking at this solution carefully.

Besides, some additional thought on why the datasheet (table 1) list only rise but not fall time:

upon ON at ON/OFF pin, Q2 is turned on, so "explicit C1" or "parasitic capacitance (denoted by C1') between gate and drain" will be connected in serial with RS, so this open path (RS) allows C1 or C1' to be charged, and the voltage on C1(C1') changes by Vin*(1-Exp(-RS*C1*t));

upon OFF at ON/OFF, Q2 is off so there is now only a path R1-C1 between (VIN and VOUT) for C1 to discharge. Granted we can make R1 small (as you suggested), the discharge of an RC circuit follows Vin*Exp(-RS*C1*t)

The key difference is therefore between 1-Exp(-RS*C1*t) and Exp(-RS*C1*t) !! If we plot this we see that for example if we take 15% of a period T to reach 90% in the "ON" operation, we need another 85% of T to reach 10% in the "OFF" operation.

So this exponential growth/decrease rate issue is the whole reason that fall time is much longer than rise time? Does it make sense?

If so, I guess that (1) you solution will work;  (2) replacing C1 by a resistor will also work, perhaps even better.

Could you give more thoughts on this?

Hui

Ron,

Ron Michallick said:

Hui,

For fastest turn off [try any/all].
1) Lower C1. I know you already tried no cap.
2) Lower R1. This helps pull the internal PMOS gate high faster.

3) Add an external PMOS across R1 (source on VIN, drain on R1C1 node). The gate goes to ON/OFF input.
This works if ON/OFF runs at 0V to VIN voltage levels. With 0V input new PMOS shorts out R1 and shorts internal PMOS gate to source.

In numerical simulation if we make R1 excessive small (like 10 or 20ohm) this leads to convergence issues, however, the fall time does improve very significantly.

For the real device operation (no numerical issue) if we could solve heat dissipation issue (such as using large area resistors), would it make sense that we replace R1 and RS with much smaller counterparts, such as R1/100 and RS/100, or even /1000, keeping the ratio is unchanged, in hope to get best fall time response?

Please point out if this might lead to any other side effect / hazard and the necessary caveats.

Hui

Hui,

R1 can't be too low or the on VGS for the pass PMOS will be low.  |VGS| = VIN * R1 / (R1 +12.5k)

I suggest helping the turn off externally. Here is an idea using a PNP or PMOS helper.