I am designing a high efficiency (>85%) 42-65V, 12A charger based on PFC-PWM configuration using Phase-shifted Full-Bridge topology (UCC28950). I have some design queries which are mentioned below (I've followed the SLUA560B design document for my design):
- What could be the reason behind using a fixed VDSON = 0.3V (page 3 of SLUA560B)?
- What could be the reason behind using fixed DMAX = 0.7 (page 3 of SLUA560B) with a preceding PFC stage; also how much DMAX changes without PFC stage?
- I'm unable to exactly understand the relevance of Vdrop (page 13 of SLUA560B) and its role in determining input capacitance. From what I understand it accounts for the period when ZVS is in process and we don't have connection between positive and negative on the primary side; during this period the capacitance must be able to provide output voltage regulation until ZVS is achieved.
- Since mine is a charger design with output voltage range 42V through 65V (unlike fixed output design in the SLUA560B document), which value of VOUT do I use in my calculations?
- How severe can the impact of LMAG on my design be, in terms of efficiency, losses, heat, if I change it by some 1.6mH?