TPS2492 power limit disable

When using an electronic load, the constant current action can force the hotswap output below system ground (the e-load attempts to keep the current flowing even if it must reverse the output voltage to do so). If this voltage reversal exceeds -Vgs(th) of the FET, then the FET can turn back on and be damaged. You can find further description in the TPS2492 datasheet on page 25 (output clamp diode section).

If the SOA protection feature of TPS2492 is not used, then you will need to find a larger FET that can withstand VIN (V) at ILIM (A) for Tfault time. Under the condition you describe (28V and 10A), the BSZ042N06NS can only withstand this power for ~100us at 25C.

With Cfault = 0.1uF the fault timer will run for ~16ms which is too long for this FET. If you use the power limit feature (FET SOA protection), then you may be able to get this FET to survive this overload condition (using a resistive load which will not pull the output below ground). You can use the TI spreadsheet design tool to assist you.

http://www.ti.com/lit/zip/slvc033

Eric'

first I want to thank you for your fasr response.

My problem is that I can’t change the package cause the board is already assembled.

I used LT4256-1 before and I chose TPS2492 because the integrated current monitor.

At the LT4256-1 in over current the FET transfer the current until the timer reached the timeout. The current isn’t limited.

How can I get the same characteristics as in LT4256-1 at the TPS2492?

I also got the TPS2492-EVM and did some tests and the results I got are very disturbing.

I worked with pull-up of 47K between prog and vref. R3 and R5 are NA. R7 is 7 mOhm

At constat current (7A) the FET toggled on anf off untile the timer riched 4V.

This deosn't meet the data sheet.

Shmuel

Eric,

Typo- R7 is 10 m Ohm

Was the overload still applied using the electronic load? Can you try with a resistive load? Also provide scope waveforms showing the overload event. If possible, plot input voltage, output voltage, current and the timer voltage.

In your test setup, how do you connect the input power supply to the hot swap board? Sometimes with long test cables, the input voltage can droop low enough to be below TPS2492 UVLO (~8.7V) or de-assert the EN pin. Under these conditions, the protection will not behave as expected.

Eric

I attached few pictures.

1. The setup.

2. Evaluation Board.

3. Power Limit- Response for constant current load (10A).

4. Power Limit- Response for constant resistive load (1 ohm).

At the Eval. board is with power limit (47K between PROG and VREF and 10K between PROG and GND) and the capacitor timer is 0.1uF.

5. NO Power Limit- Response for constant current load (10A).

6. Zoom of the above-

7. NO Power Limit- Response for constant resistive load (1 ohm).

At the Eval. board is without power limit (47K between PROG and VREF ) and the capacitor timer is 0.1uF.

I hope it will help to understand the problem.

I expected to see at the output a stady voltage until the timer reach 4V. Am I worng with my expectations?

Eric,

I'm still waiting for your response.

Thanks

Shmuel

Thank you for the well detailed photos and plots. I did not see VIN droop so it seems we can rule that out. I still believe that there is an interaction with the electronic load. That is a common test problem with an active hotswap circuit. Can you try the resistive load right at the EVM output terminals and report the results? You can also just apply a direct short at the EVM output terminals if you do not have a large resistor handy.

Eric,

I attached the plot of the short at the EVM output terminl:

At my board when I did a short at the output it burn the FET. This I can't understand.

Shmuel

The circuit seems to be working as expected. When the short is applied, the TPS2492 goes into current limit and the timer starts. You can see the current being regulated at the IMON pin as Vimon/Gain/Rsense or 2.4V/48/0.01 = 5A for approximately 15ms before the FET is turned off. Referring to the TPS2492EVM-003 user guide, the Q2 FET = IRF540NSPBF and figure 8 of the Q2 datasheet indicates that the 25C SOA stress applied to this FET at Vds=15V and Id = 5A should be present for less than ~10ms.

For the case above, the stress lasted for ~15ms and exceeded the SOA of the Q2 FET.

The TPS2492EVM-003 as designed with FET SOA protection (power limit enabled) keeps Q2 within the safe operating area when the output is shorted. Plim = Vref x R3 / (R2+R3) x 10 x Ilim = 26W. When the output is shorted, Vds = 15V and TPS2492 will regulate current at Plim / Vds = 1.74A for 16ms. This stress level for Q2 is within the SOA with plenty of margin.

Hopefully this explanation can help to either choose a more robust FET or consider using the TPS2492 FET SOA protection feature.

Hi Eric,

The design is already done and in the board I can't change the FET fotprint.

Is there any way to disable the current limit of the device?

I have a current neasurment that goes to controller, and by software I can turn off the switch when I detect over current.

Shmuel

Eric,

But in that way I'll lose the current measurment.