We’ve had very high fallout with these parts on our manufacturing floor. We recently had to hand replace every single part of the 21 used on each of our cards as we were having widespread opens and shorts—some latent, but many not. We returned many samples to TI for failure analysis and the conclusion was that either our PWB footprints were wrong, or something in our manufacturing process was wrong.
We received and reviewed TI’s Strategies for handling WCSP parts presentation (TI_WCSP_Handling_SK_2012_Nov.pdf) and TI Wafer Chip Scale Package SMT Guidelines, June 2011. We’re in the process of designing a test card that will have some of our old footprints, and many new footprints that are based on TI’s guidance. We’ll use this test vehicle to hopefully replicate our failures with the old footprints, and prove that with the TI-recommended footprints, we can use these parts without high failure rates.
In our application, the device pins are typically connected on the PWB in 1 of 2 ways. They are either enveloped in copper pour (for the VIN and VOUT pins), or they are connected by a Microvia-in-pad (for the ON and GND pins). We rarely find ourselves escaping the pins using traces in an HDI design (i.e. blind and buried vias) which is where these parts are typically used. Both of the aforementioned TI documents were silent on the use of Microvias in the pads for these parts.
Q1. Please provide any applicable guidance and/or cautions related to the use of Microvia-in-Pad for these parts.
At this writing, we are assuming that if the Microvia pad is larger than the TI-recommended pad size for the pin, then we would apply soldermask to create a soldermask defined pad based on TI’s guidance in the TI Wafer Chip Scale Package SMT Guidelines document (pages 6-7). If the Microvia pad is smaller than the TI-recommended pad size for the pin, then we’d just use the TI-recommended pad size.
Q2. Please advise if our assumptions regarding TPS22924CYZPR pad size with an embedded Microvia above are incorrect.
In either case, we assume the use of a Microvia (i.e. laser drilled hole that’s ~5 mils in diameter, and ~2-5 mils tall, connects the outer layer to the next layer in, and is typically 100% filled with copper) is acceptable for these parts. We include a PWB drawing note that requires our fabricator to ensure the Microvia dimple does not dip down more than 1 mil into the pad. We don't specify a limit for a dimple that would protrude from the pad (i.e. if the Microvia plating were to produce an outward dimple); we rely on applicable IPC specifications to limit these, but in practice, we don't see many outward dimples. They typically are dimples that extend down into the pad.
Q3. Please advise if our assumption that it's acceptable to embed a Microvia (as described above) in the pad for the TPS22924CYZPR is incorrect.
