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TPS3808G01 /RESET output not going high

Other Parts Discussed in Thread: TPS3808

Hi,

My customer has TPS3808G01 implemented in several designs.  On occasion, the TPS3808G01 will hold /Reset active and keep it there, even though the criteria for releasing /Reset have been met.  My customer claims that washing the circuit board fixes the problem.  Here is my customer's description of the problem:

Here’s an example of one of the circuits we have (This circuit is not the only one that causes problems, however.):

 2086.TPS3808 Schematic.TIF

(NOTE: I pointed out that the schematic does not show a 10nF cap on the SENSE input.  Customer has since added the cap; no change)

The two outputs, RSMRST~ and PWR_BTN~ feed directly into the Via CX700 system processor.  I have measured and verified that the MR input is at 3.3v, the VDD power rail is 3.3v, the SENSE pin is over 0.405v (usually between 0.480 and 0.6v depending on the specific circuit).  On one of my boards I have also disconnected R147 and R572 to see if somehow loading is causing the problem, and the reset still doesn’t go high.

 

On another board, with a different circuit using the TPS3808, the RESET~ output feeds into two IC’s (a 7400 series AND gate and a Multivibrator Reset input).  I found that if I disconnected both loads the 3808’s reset would finally drive high.  This shouldn’t be the case because both inputs are high impedance.  Perhaps there’s some capacitive load requirement the 3808 spec doesn’t mention?

Are there any known problems with TPS3808?

Thanks,

Rick Rubio

  • Hi Rick,

     

    Thank you for all the information you’ve been able to provide.  However, I think we will need a little bit more information to tackle this problem.

     

    You mention that the customer is using the TPS3808G01 in several designs.  Is this issue present on all of them, or just a few?  You also mentioned that it is an occasional problem—do you have any more information about when the problem occurs?  Is there a certain set of conditions that the customer has identified to make the issue appear?

     

    The customer also says that washing the board fixes the problem.  I am confused by this—do you know what the electrical impact of washing the board might be?  Before the boards are washed, what kind of condition are they in?  Could any of the devices/components be shorted out?

     

    I have looked over the schematic, and it seems to me that as long as /RSMRST and /PWR_BTN go to high-impedance pins everything should function normally.

     

    When the customer is measuring the various voltages on the board (/MR, VDD, and SENSE), are they using a voltmeter or an oscilloscope?  If only using a voltmeter, there may be some time-domain behavior that they are missing which might be of some interest.

     

    To answer your questions,

    • There is not a capacitive load requirement.  Additional capacitance on the RST line should slow the rise time of the reset signal, but I don’t see how it could prevent the low-to-high transition entirely.
    • I don’t know of any problems with the device.

     

    Again, thanks for all the valuable information so far.

     

    Best regards,

    Max Robertson

    Linear Power Applications

    m-robertson@ti.com

  • Hi Max,

    Thanks for your response.  See answers to your questions below:

    Thank you for all the information you’ve been able to provide.  However, I think we will need a little bit more information to tackle this problem.

     

    You mention that the customer is using the TPS3808G01 in several designs.  Is this issue present on all of them, or just a few? 

    The issue has been seen in 3 out of 3 designs.

     

    You also mentioned that it is an occasional problem—do you have any more information about when the problem occurs?  Is there a certain set of conditions that the customer has identified to make the issue appear? 

     

    The problem is intermittent.  We have been unable to ascertain a set of conditions under which we can reliably and consistently duplicate the problem.

     

    The customer also says that washing the board fixes the problem.  I am confused by this—do you know what the electrical impact of washing the board might be?  Before the boards are washed, what kind of condition are they in?  Could any of the devices/components be shorted out?  

     

    It confuses us as well; and I know it sounds a bit absurd.  Before washing/scrubbing, the surrounding area often seems to have some flux residue, although I am not certain if this is universally the case.  Otherwise, everything is in good condition, good solder joints, etc.  Even after scrubbing the area with alcohol (or water) the problem sometimes persists and, then, after a bit more scrubbing the problem seems to go away.  If it is a shorting-out problem, it seems odd that only this component (in multiple places on the board) would be affected.  In addition if, say for example, the SENSE pin were shorted to GND, we should expect to see the SENSE voltage lower than the threshold, which is not the case.

     

    I have looked over the schematic, and it seems to me that as long as /RSMRST and /PWR_BTN go to high-impedance pins everything should function normally.  Agreed.

     

    When the customer is measuring the various voltages on the board (/MR, VDD, and SENSE), are they using a voltmeter or an oscilloscope?  If only using a voltmeter, there may be some time-domain behavior that they are missing which might be of some interest. 

     

    We have been using a scope the entire time.

     

    To answer your questions,

    • There is not a capacitive load requirement.  Additional capacitance on the RST line should slow the rise time of the reset signal, but I don’t see how it could prevent the low-to-high transition entirely.  Good to know.
    • I don’t know of any problems with the device.  That’s what we wanted to make sure about.

     

    One additional question that comes to mind is what is the sensitivity of the SENSE pin?  I notice the datasheet indicates 2% accuracy and up to 3% hysteresis.  As you can see from our circuit, when our 3.3v input voltage rail reaches 2.79v (corresponding to Vith = 0.405v), the reset output should de-asssert.  When fully ramped up, our 3.3v rail should correspond to 0.478v on the SENSE input, which is well above the threshold voltage.

     

    We haven’t noticed any transients that drop down anywhere near the 0.405v threshold, but is it possible that this input is more sensitive or less accurate than 0.405v + 2%?  We haven’t tried it, but would our circuit benefit from increasing the voltage seen on the SENSE input (by adjusting the resistor divider)?  Is there any problem powering the device from the same voltage that is used on the SENSE input?

    Let me know if you need more clarification.

    Thanks,

    Rick

  • Have you tried pushing on the IC or individual pins when it is not functioning properly?

  • With regards to the SENSE pin accuracy, the information in the datasheet is correct.  The nominal negative-going input threshold is .405 V, and it is accurate within +/- 2%.  /RESET is asserted when the voltage at SENSE drops below this threshold.  The positive-going threshold (which must be exceeded for /RESET to de-assert) is up to 3% greater than the negative-going threshold.  Therefore, the maximum possible voltage level required at the SENSE pin for /RESET to go high is (.405 V)*(1.02)*(1.03) = .425 V.  If you assume the worst-case variance of the resistors in your divider (e.g. R576 is 1% higher than nominal and R577 is 1% lower than nominal), this translates to a Vdd of 2.987 V.  This is still a good bit below 3.3 V, so I don't think device accuracy is what is keeping /RESET low.

    To answer your other question, there is no problem configuring the TPS3808G01 to monitor its own power rail.  In fact, this is pretty common usage.

    I second Scot's suggestion above.  It would be a good idea to see if this issue's origin is mechanical rather than electrical.

    Best regards,
    Max Robertson