Dear Engineers,
I'm designing TPS40057 power supply, and to avoid any problems I'm using reference design in http://www.ti.com/lit/pdf/sluu186.
Please review EVM datasheet in link for following questions:
1.Why is power pad isolated from gnd planes in layer 2 and bottom layer?
2. Why is gnd plane missing under SW plane in layer 2?
3.Why are input capacitors from both sides of high side FET? Is there any reason why to not have all input capacitors in one hive?
Thank you.