[LP2951-50]For behavior during power-up of the LP2951-50

Tomoaki-san,

Do you know the input voltage ramp rate and minimum load current?
Is the output set to 5V, with pins 1 & 2 shorted and pins 6 & 7 shorted?
What are the capacitors (if any) on pins 1, 7, and 8.

Hi Ronald,

I am are going gonna waveform and schematic, but trouble is to not be up.
Because it described in the text, it is, but you will worry whether well transmitted.

Circuit configulation
・8pin (input) is going to 0V to 13.5V by 1us/V.
This pin is connected to GND by 1.1uF capacitor .
・6,7pin(FB and VTAP) are shorted. No capacitor connected.
・5pin(IERROR) is open.
・4pin(GND) is conected to GND directly.
・3pin(SHUTDOWN) is connected to GND by 10k ohms chip resister.
・1,2pin(OUTPUT and SENSE) are shorted and connected to GND total 1.42uF capacitor.
This pin is 3loads and each load current is under 1mA. Total load current is under 3mA.

Behavior
・Input voltage up to 13.5V by 1us/V.
Then output voltage is reached to 6.5V until 80us.
After then, output voltage is settled to 5V over 4ms.

Do you will see the situation with this?

Thanks.

Tomoaki-san,

A little overshoot is expected, but the amount observed is more than expected.
I will schedule some lab time this week to verify the issue.

Tomoaki-san,

I also saw a large power up overshoot with your input rise time and capacitors.

Increasing the output capacitor (up to 10uF) reduced the overshoot, but did not eliminate it.

A 150pF capacitor from pin 7 to pin 1 eliminated the over shoot and also improved load transient response.

LP2915-150pF.TIF

Hi Ronald,

Thank you for your reply.
I will your advice to reference.

There is additional question about behavior for LP2951-50.

At first,LOAD TRANSIENT RESPONS VS TIME graph is rested in the datasheet.
Will how much slew rate of output load transient this case?

In the actual measurement,output overshoot is 0.63V at rising and falling slew rate is 64mA/us,transient current is 70mA, Cload is 0.47uF and Vout is 5V.
Is it normal?

I would like to know wether this behavior is correct and overshoot is how much change due to the difference of the slew rate.

thanks.

Tamoaki-san,

The data sheet output current slew rate is very fast, ideally instantaneous.
Before the pulse, LP2951 was providing fixed current to load and capacitor current was zero.
Upon fast increase in load current, the capacitor provides the current and the LP2951 "slowly" increases current to match load and replenish capacitor voltage.
Upon fast decrease in load current, The LP2951 will still provide the previous current level. The capacitor will absorb the unneeded current until the LP2951 realizes the voltage is too high the LP2951 will stop providing current. Then the load will slowly discharge the capacitor to the correct voltage and the LP2951 will provide the new load current.

The LP2951 is LDO and like most true LDO devices, they are voltage controlled current sources. It take a finite time to change the output current. If load slew rate is slow compared to LP2951 response time then overshoot will be minimized. If capacitance is large then overshoot will be smaller.

Hi Ron,

Thank you for your reply.

I understood that overshoot and undershoot of load transient under my term are normaly behavior.

In the case of fast increasing load current , the output voltage is smaller.


Although it is matter of over-upon power-up that was the question before, please tell me the principle of overshoot is reduced when PIN1 and pin7 are connected by capacitor.

I understand that response is improving but I don't have idea to eliminate the overshoot.

Regards

Tomoaki-san,

With no capacitor 1 to 7, power up turns on output at full current because feedback (7) is below target (of 1.25V). Output stay full on for the whole range of VOUT (0V to 5V). When VOUT reaches desired voltage, feedback will turn off output but this takes a little time. During this time VOUT goes too high.

With a capacitor 1 to 7, power up turns on output at full current because feedback (7) starts below target (of 1.25V). Output stays 'full on' only until VOUT passes 1.25V, past this point the capacitor (that started at 0V) has pulled up feedback (7) and the output current will be reduced. The rest of the VOUT increase is set by the time it takes the capacitor to charge up the final voltage set by feedback resistors. Because the reduction in LDO current is controlled and not abrupt, the response is dampened with no over shoot.

Hi, I have a similar circuit arrangement to Tomoaki-san. I could not work out why my output voltage slowly ramped up from around 4V to 5V over a minute or so. The voltage regulator was the simplest part of my design and yet it was the only part not working correctly! After chasing my tail for a while I realised that the flux I was using (water soluble) was conductive and there was residue under the LP2951. This was affecting the operation of the regulator. Once I cleaned the flux from under the part it worked correctly. Simple, but it took a little while to solve the problem. Even a small amount of moisture around the part can adversely affect the output. This was the only post I found that talked about startup issues with the LP2951 so I thought I would document my experience so it hopefully saves someone else the time if they have this silly problem too! (or anything else that causes a partial short around the LP2951).

Regards, Antony.

Antony,

Really appreciate you adding content to our forums. Please feel free to post in any forum about questions you may have about our devices, and we are always happy to help support!

Best,
Michael