Hi
We have some following questions from customer.
1. Does the Islope depend on Fsw? It looks that the peak of the current decreases when increasing the FSW.
2. Is the voltage of SSSR provided from internal VREF? The voltage of SSSR is greater than the voltage of VREF. （SSSR=VREF+0.5V）
3. At Page.10, the FET gate connects to DRIVER LOGIC. However at Fig22 the gate connects CLK. Which is correct?
4. How much is the R which is connected to PWM comparator.
5. Is the ON period and timing of FET inside of RAMPpin same as the CLK timming?
Please let me know if you have any questions.
Regards,
Koji Hamamoto
