Hi all,
I have two designs D1 and D2 such that both of them operate at the same clock frequency 148.5 MHz and synthesized over Zynq ZC706 board
For D1 the resource utilization was as following:
Slice Logic Utilization: Number of Slice Registers: 24,735 out of 437,200 5% Number of Slice LUTs: 31,587 out of 218,600 14% Slice Logic Distribution: Number of occupied Slices: 12,360 out of 54,650 22% Specific Feature Utilization: Number of RAMB36E1/FIFO36E1s: 18 out of 545 3% Number of RAMB18E1/FIFO18E1s: 77 out of 1,090 7%
While for D2 was :
Slice Logic Utilization: Number of Slice Registers: 49,848 out of 437,200 11% Number of Slice LUTs: 77,056 out of 218,600 35% Slice Logic Distribution: Number of occupied Slices: 27,116 out of 54,650 49% Specific Feature Utilization: Number of RAMB36E1/FIFO36E1s: 18 out of 545 3% Number of RAMB18E1/FIFO18E1s: 78 out of 1,090 7%
For total Power estimated by Xpower Analyzer:
For D1 was 1593.51 mW and for D2 was 3931.84 mW
BUT when I measured them using the TiFusion tool for different rails for 10 min Data logging it was
For D1 For D2: Vout_1 1,00 1,00 Power_1 1,013778177 1,223831187 Vout_2 1,8 1,8 Power_2 0,296198383 0,302336234 Vout_3 1,5 1,5 Power_3 0,055671582 0,057512424 Vout_4 2,5 2,5 Power_4 0,271544563 0,232731928 Vout_5 3,3 3,3 Power_5 0,206161794 0,206130838 Vout_6 1,7 1,7 Power_6 0 0 ================================================================= sum 1,8433545 2,022542611
So Why does the Power estimated by XPower is differing so much from what I have measured practically by TiFusion ??
What are the acceptable area utilization of FPGA to get accurate practical measurements ??
Is there some configurations that I should do for the tool to improve the accuracy of the measurements ??