• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 63 subscribers
  • Views 1054 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC28070EVM creates unexpected PFC PWM waveform

Bill Mather
Prodigy 20 points
Other Parts Discussed in Thread: UCC28070, UCC28070EVM

Hi,

We intend using the UCC28070 in a SMPS application and are using the UCC28070EVM to test and develop our product.

One of the tests we did was to verify the PFC PWM signals and the PFC operation. What we found was unexpected.

We expected to find the PWM duty cycle varying slowly over a number of cycles, and that the PWM duty cycle could be directly correlated to the input AC voltage.

The duty cycle we observed was inconsistent with our expectations in that it contained wide excursions each half cycle of the AC mains.

The test was a very simple test - connect a resistive load (660 ohms) to the EVM and measure the PWM duty cycle for a nominal 110VAC (50Hz) and 240VAC (50Hz) after PSU was stable after power on.

A 100MHz logic analyzer was used to capture gate switching of the IRFB11N50A inductor FETs Q1, Q2. Both gate signals were captured to confirm duty cycle data. The data capacity of the analyzer allowed the capture of the waveform over 1.5 AC 50Hz cycles. The PWM period was observed to be constant at approx 200KHz (505 * 10nS), giving nearly 2000 PWM periods per half AC cycle.

To make sense of the data, the data was plotted, with the results resembling the shape of a Viking Helmet. The 110VAC plot appears much 'cleaner' than the 240VAC plot, in that there is a short 'reversal' in the duty cycle appearing twice each cycle in the 240VAC plot.

Attached are 2 plots, one for 110VAC 50Hz 660 ohm load, one for 240VAC 50Hz 660 ohm load. The scale units are in the 10nS units of the logic analyzer capture.
The X axis is time from trigger, while the Y axis is the PWM pulse width (duty cycle) for the Q1 gate.

We don't understand the waveform we captured.

a. We expected an essentially constant PWM duty cycle since the load is resistive and constant.

b. We expected the PWM duty cycle to vary slowly, if it did so, over 10 AC cycles, not dramatically several times per half cycle.

c. We expected the PWM duty cycle to directly reflect the input AC voltage, which could be presumed to be constant over a 2 cycle AC period.

Help requested:

We need to understand WHY we are getting these waveforms. Our expectations are based on our previous designs (which are smaller, being 120W and less). Could you please assist us so that we can go forward with our design.

Hi,

We intend using the UCC28070 in a SMPS application and are using the UCC28070EVM to test and develop our product.

One of the tests we did was to verify the PFC PWM signals and the PFC operation. What we found was unexpected.

We expected to find the PWM duty cycle varying slowly over a number of cycles, and that the PWM duty cycle could be directly correlated to the input AC voltage.

The duty cycle we observed was inconsistent with our expectations in that it contained wide excursions each half cycle of the AC mains.

The test was a very simple test - connect a resistive load (660 ohms) to the EVM and measure the PWM duty cycle for a nominal 110VAC (50Hz) and 240VAC (50Hz) after PSU was stable after power on.

A 100MHz logic analyzer was used to capture gate switching of the IRFB11N50A inductor FETs Q1, Q2. Both gate signals were captured to confirm duty cycle data. The data capacity of the analyzer allowed the capture of the waveform over 1.5 AC 50Hz cycles. The PWM period was observed to be constant at approx 200KHz (505 * 10nS), giving nearly 2000 PWM periods per half AC cycle.

To make sense of the data, the data was plotted, with the results resembling the shape of a Viking Helmet. The 110VAC plot appears much 'cleaner' than the 240VAC plot, in that there is a short 'reversal' in the duty cycle appearing twice each cycle in the 240VAC plot.

Attached are 2 plots, first is 110VAC 50Hz 660 ohm load, second is 240VAC 50Hz 660 ohm load. The scale units are in the 10nS units of the logic analyzer capture. Note 110VAC PWM excursion is to 3.5/5uS, while the 240VAC excursion is only 2.13/5uS.
The X axis is time from trigger, while the Y axis is the PWM pulse width (duty cycle) for the Q1 gate.

We don't understand the waveform we captured.

a. We expected an essentially constant PWM duty cycle since the load is resistive and constant.

b. We expected the PWM duty cycle to vary slowly, if it did so, over 10 AC cycles, not dramatically several times per half cycle.

c. We expected the PWM duty cycle to directly reflect the input AC voltage, which could be presumed to be constant over a 2 cycle AC period.

Help requested:

We need to understand WHY we are getting these waveforms. Our expectations are based on our previous designs (which are smaller, being 120W and less). Could you please assist us so that we can go forward with our design.


　

  • 0
    Genius 3295 points

    .Bill,

    The graphs make no sense to me because I am not sure what "data" you are trying to make sense of. Is this gate drive voltage? Can't be with that high a magnitude, you would have blown out your MOSFETS.  I am assuming the horizontal scale is time and vertical scale is voltage. Is this the rectified input voltage?

    One important fact you need to be aware of is that you have a very, very, light load. I am surprised you see any waveform output at all with a 660 ohm load. Since the UCC28070 is a continuous conduction mode PFC, it is not meant to be run at such a light load. That may explain some of the weirdness in your waveforms. 

    You should test at about 20% full load, or better yet check the EVM user guide. It should have all the waveforms and test set ups you need to use to measure everything.

    I would ditch the logic analyzer too. You need to get an oscilloscope to measure the waveforms in real time. Logic analyzers are used to measure logic signals. They have really bad dynamic range and can't measure voltage ranges from mV to 100Vs like an oscilloscope. 

    I will try to answer your general questions concerning duty cycle and the AC input voltage: 

    " We expected an essentially constant PWM duty cycle since the load is resistive and constant:"

    There is no reason I can think of for you to expect a constant duty cycle. The AC input voltage varies and the boost adjusts it's duty cycle, D, to try a output a constant DC voltage. So when in the input is low, the boost converter DC gain needs to be high. The DC gain of a boost converter is 1/(1-D). Therefore at low input voltage the duty cycle is high. As the input voltage increases the duty cycle D, decreases, until it reaches it minimum at peak input AC voltage

    b. We expected the PWM duty cycle to vary slowly, if it did so, over 10 AC cycles, not dramatically several times per half cycle.

    c. We expected the PWM duty cycle to directly reflect the input AC voltage, which could be presumed to be constant over a 2 cycle AC period.

    The AC voltage output from the rectifier varies from 0 V to approximately 150 to 180 V with a 115 V AC input.

    I added some PFC simulation screenshots for your review:

    The top purple waveform is the DC output voltage. The green waveform is the rectified AC voltage that is input to the PFC boost circuit. The red waveform is the gate drive signal to the MOSFET with widely varying duty cycle. The duty cycle is maximum near the "cusps" of the AC input voltage and goes to zero after the peak. The zero duty cycle is due to the slow response of the PFC. 

    Second waveform is a close up of the duty cycle and the input, rectified, AC voltage near the zero point or cusp.

    The third waveform shows the duty cycle at peak VAC:

  • 0 in reply to Chuck Sampson
    Prodigy 20 points

    Hi Chuck,
    thanks for your reply.

    Here are some answers to the points you raise:

    a. X-axis is time elapsed, in 10nS units.  Y-axis is gate ON time, in 10nS units.
         As your MOSFET Gate Voltage traces show, the voltage is a ON/OFF voltage 0v to voltage set by D13 (BZX84C13-7)

    b. the UCC28070EVM outputs 390VDC - with a 660 ohm load, giving 230W, being 2/3 of the EVM 300W continuous rating. This load was chosen (guessed) to be outside the bounding areas where the PWM duty cycle ON time could drop to zero and where the PWM duty cycle could be constantly ON, for the 110/240VAC inputs.
    The load is resistive, to remove any reactive factor influence on the measurements.

    c. My CRO is a 100MHz device with limited internal data storage. The analyser was set up to collect the period and duty cycle data over at least one full cycle.

    Our expectation was that the PWM duty cycle would be relatively constant over 10 AC cycles, or at worst, be cyclic in a simple relationship with the input AC sine curve.

    I think there are 2 issues:

    1. Why the multiple PFC PWM duty cycle excursions, and

    2. Variation of PFC PWM duty cycle with a constant resistive load.

  • 0 in reply to Bill Mather
    Genius 3295 points

     The duty cycle varies because the input voltage varies, as I explained and showed in my previous post.

    You are right about the 660 ohm load. That should be fine.That was an error on my part.

    The load has very little to do with the duty cycle variation unless it is stepped, and some variation of the duty cycle  will occur due to losses if the load resistor is decreased. .

    A constant load does not equal a constant duty cycle. The duty cycle equation for a boost converter is 1/(1-D) and D is Vout/Vin, so if Vin is small, the DC gain is large and when Vin is large, the DC gain is small as shown in the simulation plots I showed you above. 

    -Chuck