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TPS62177 self-destructive tendency

D E Ungar
Intellectual 680 points
Other Parts Discussed in Thread: TPS62175, TPS62177

It appears that the TPS62175 / TPS62177 is severely vulnerable to self-destruction.  Several other posters have reported simple mechanisms which induced the chip to destroy itself:
TPS62177 grenades on power up the second time, but works on the first.
https://e2e.ti.com/support/power_management/non-isolated_dcdc/f/196/p/370421/1302868#1302868
TPS62177 breaks on input voltage change
https://e2e.ti.com/support/power_management/non-isolated_dcdc/f/196/p/263694/922133#922133
first attemp at switching dc-dc ends in smoke :(
http://forum.43oh.com/topic/5786-first-attemp-at-switching-dc-dc-ends-in-smoke/

While initially testing a design incorporating the TPS62177, I touched an area of the PCB several inches from the TPS62177 and felt a small static discharge.  Within seconds, the TPS62177 was emitting smoke.  The point I touched could only have led to a conduction path to system ground or to the +24V rail feeding the TPS62177.  When the TPS62177 was removed and a TPS62175EVM evaluation module jury-rigged in its place, the system ran fine - the op amps and DSP, which I would have expected to be more delicate, were not significantly affected.

I added a transient voltage protector diode (Vishay TransZorb SMCJ24A) to the +24V rail in the next revision of my product.

I recently discovered the first of the new boards (with TransZorb) non-functional after working fine earlier in the day.  I and an associate each remember briefly transmitting a small static shock to one of the board's mounting standoffs which could only have arced over to system ground, the +24V rail or a signal driven by a chip powered by +24V and only connected via a chain of intervening ICs to the +3.3V output of the TPS62177 (which is carried by an isolated island in the internal power plane of the PCB).  Neither of us witnessed the actual failure, so I cannot say whether there was any smoke, but later examination revealed a distinct pinhole in the top of the TPS62177 package near pin 3.  When an external +3.3V supply was subsequently connected (with the TPS62177 still in place), it was dragged down to ~1 V at its 1 A current limit.

Because both of these failures were catastrophic and occurred while the chip was powered, I believe they are evidence of some form of latchup.

Are there reasonable precautions that must be taken when using this chip, beyond the whopping big 1500W TransZorb I have already provided?  Is T.I. aware of how vulnerable this chip is and is a corrected stepping available?

  • 0
    TI__Guru**** 150820 points
    Almost all integrated circuits have built in ESD protection these days. But this protection can only do so much. Our newer datasheet's have this note on the ESD table to simply explain what the ESD protection is designed for:
    (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
    (3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process

    The point is that we're expecting the user to observe reasonable ESD protection precautions when handling the devices. If a spark is seen and/heard, it is a huge ESD event which is likely well beyond the ratings of the device. Most ESD occurs without seeing or hearing anything. These are at a lower level.

    If the end customer can touch the PCB and/or components, then you should design your system to withstand this type of ESD. During development, it is extremely common and mandatory at many companies to wear ESD wrist straps, etc. when working with bare boards.

    In regards to the three posts you referred to, these are fairly easily answered in those threads I think. The first and third threads are from the same person. In the third thread, he seems to have installed the wrong device version while in the first thread, his input power supply overshot past the ratings of the device. In the second thread as well, the user clearly violated the absolute maximum rating of one of the pins by an erroneous connection. We do expect our customers to operate the device within its ratings as stated in the datasheet for reliable operation.
  • 0 in reply to Chris Glaser
    Intellectual 680 points

    Chris,

    Thank you for your reply. I agree that good ESD practice is vital. What still troubles me, however, is twofold:

    1) While I recognize that a perceptible spark is, indeed, a major ESD event, in both failures that we have experienced they occurred at an area of the PCB somewhat isolated from the TPS62177 and still caused catastrophic failure, even after the application of a hefty TVS diode to protect the most exposed node. Other ICs which I would have expected to be more delicate than a power converter recovered and continued to function when the TPS62177 on the first PCB was removed and replaced with an EVM board.  The TPS62177 seems to be the weakest link in the chain even though it is a "power" IC.

    2) More significantly, while all ICs are vulnerable to damage due to the energy delivered by an ESD hit, the TPS62177 appears to be exhibiting a latchup mechanism in which a minor amount of energy delivered to it results in a greatly amplified flow of energy from the input power source and the chip quite literally and quite dramatically self-destructs. What may be a minor assault if received when the part is not powered up, perhaps slightly weakening and reducing the life of a part, is instead turned into catastrophic failure. This is why I cited the other three postings - they indicate that the part is very vulnerable to casual mistreatment with drastic consequences. I suspect that, while powered up, an ESD hit below its rated robustness might be sufficent to trigger this self-destructive behavior.

    Is Texas Instruments addressing this weakness?

    Regarding the lower ESD toughness in "newer datasheets," the current (SLVSB35B –OCTOBER 2012–REVISED JANUARY 2014) TPS62177 datasheet at http://www.ti.com/lit/ds/symlink/tps62177.pdf specifies

    ESD rating(3)
    HBM Human body model 2 kV
    CDM Charge device model 0.5 kV
    (3) ESD testing is performed according to the respective JESD22 JEDEC standard.

    Do the new, lower limits also apply to the TPS62177?  They are really quite wimpy, especially for a power management IC.

  • 0 in reply to D E Ungar
    TI__Guru**** 150820 points
    I'm not sure what you mean by saying 'power IC'. This is a power supply IC. But I don't see a reason why a power supply IC should fundamentally be any different than any other silicon device as far as robustness. We design the silicon to withstand a certain voltage and, just like any silicon, it will break if you go above that voltage.

    1) There's no telling where the ESD went on the circuit board, into what nodes, etc.

    2) I wouldn't classify violating the clearly stated absolute maximum ratings of the IC as a 'casual mistreatment'. If you put a 100W bulb in a 40W socket, I would expect something to go wrong. This is the same as applying a voltage greater than the silicon is rated for, as happened in two of the threads.

    The ESD ratings are device specific and I did not imply that we are changing ours, have changed them, or are planning to change them. What I did say was that the new datasheet format (which the TPS62177 will one day have) more clearly explains what the ESD protection is designed for. It is not designed to protect against lightning strikes but is designed to protect against small ESD events that can occur in ESD protected areas, during manufacturing, etc.

    It's difficult to prove that ESD was the cause behind any failure, so I recommend examining several things in your design that frequently cause failures of any SMPS: check your PCB layout against the recommendation in the datasheet and look at the input voltage to the device with a scope and see if it ever exceeds the IC's limit.

    You are also welcome to order the EVM and test the device with a known good layout in an isolated configuration.
  • 0 in reply to Chris Glaser
    Intellectual 680 points
    Chris,

    Thank you again for your reply.

    What I mean by saying "power IC" is a component that is on the front line - it gets directly exposed to the world outside the product's case through the power input connector. Such a part will be exposed to stresses not experienced by a strictly internal component such as a DSP that connects to the outside through other components. I would expect it to be one of the more robust components, not the most vulnerable.

    I can't say for certain what caused the second failure, but I can report that a few seconds after I touched my first board with a TPS62177 and felt a mild shock, that IC literally began emitting smoke. The point of the PCB I touched was a large unoccupied module site two inches from the TPS62177 and bearing only system ground and +24V traces and power planes.

    At any rate, whatever the argument for conscientious employment of all ICs, my employer has several thousand of its other products in the field and never before have we had two of the first ten prototypes self-destruct. We clearly need to do two things: Be more conscientious in our board handling and design in a different part that is less prone to blowing out.
  • 0 in reply to D E Ungar
    Intellectual 680 points
    In an attempt to qualify use of our existing design incorporating the the TPS62177, I enclosed it in its all metal case and gave the case some +8 kV air discharge ESDs from a calibrated gun. The case is bonded to PCB ground, but there was no DC return to earth ground; any ESD had to return to ground as a transient either through the signal source via its ungrounded power supply, or through the ungrounded (2-pin AC plug) power supply powering my design.

    I don't know what path the ESD current took through the system, but the result is rather spectacular:
    www.facebook.com/photo.php;l=dc61753e04
  • 0 in reply to D E Ungar
    Intellectual 680 points

    Just figured how to embed this image: