Ron,
We found rise time is good, just fall time too long.
In order to eliminate any possible parasitic capacitance of the load, we already paralleled resistors (as a shunt) to that and this approach did improved performance a lot.
Datasheet list tables of effect of R1,C1 on rise/fall performance.
If using C1=0 still not give satisfactory performance (several microseconds of fall delay as opposed to ns scale in datasheet), can we replace C1 by a resistor as a more aggressive step?
Would this plausibly further decrease particularly fall time because one might think of a resistor as of 0 farad, and in fact facilitates current flow somehow "proactively" conducts current? Also, if this approach is allowed, is there any caveat / precaution for this because it is not shown in the datasheet example?
Hui
