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DC BIAS on BQ24650 EVM design

Victor Vargas
Intellectual 265 points

Hello Forum,

I'm Trying to understand whereas I must respect the DC bias on the capacitors regarding the EVM Design.

For example, Table 1 has the following recommended values

The EVM comes with a default .02 ohm resistor. If we respect table 1, the output capacitor must be 15uF. But in the EVM, a equivalent 11uF capacitor is placed plus a bypassing(Please correct me if its not for bypssing)  C11 0.1uF. If I choose a ceramic capacitor, due the DC bias characteristics, my capacitance will be reduced to aprox 20%-40% of the value. So I have to choose my output capacitance as C_value + C_DC_losses.  The inductor value is respected 

I want you geniuses if you can explain the following:

     1. Why the suggested capacitance is not being respected?

     2. Should my adding of C_DC_losses capacitors will improve my system ?

     3. The input capacitors of the drain of Q1 are equal to the output capacitors plus a 10uF bypass capacitor C1 (please advise if its for bypassing) . 

               3.1. Is this notion correct or should I changed it for a different  value?

               3.2. Either if the above notion is correct, should I add a capacitance equal to C_DC_losses additional to the input capacitors also?x

     4. For the input capacitors, when calculating the extra capacitance due the C_DC_losses, should I calculate the values respecting the panel output voltage or the one that is being set by the buck converter on the MPPT pin? My guessing is to do it respecting the Buck voltage that is set by the MPPT pin 

     5. Looking at other forums I have read that the noise is highly dependent of the PCB layout. Even though, if the values of the capacitors have the DC compensation, will this improve in the noise reduction?

I have the question due the DC bias because I will handle panels that are > 15 Volts

Thanks geniuses

  • 0
    TI__Expert 5565 points

    1. The values in the table is a starting point as you design your board, but the final values of the capacitance will have to be adjusted based on your load/line transients, board layout, line impedance, and the total downstream capacitance you have after the PCB (remember that the battery is also a large capacitor). The goal is to have the minimum amount of capacitance to meet all of your requirements so that the your solution size is not bigger than it needs to be. In the case of the EVM, we were OK with the transient responses with 11uF of output capacitance. The tradeoff with a larger output capacitance is your loop bandwidth will be lower.
    2. It depends. What aspect of your system are you trying to improve? See my comment in #1 above regarding tradeoffs of output capacitors.
    3. Input capacitance doesn't have to equal output capacitance. The amount of input capacitance depends on how much input ripple voltage you can withstand on your line. The amount of capacitance depends on how much ripple you can withstand on your battery voltage. Since your input current and battery current could be different values, you might need different amounts of capacitance on input/output. Also, the amount of line impedance will dictate how much capacitance you need for input and output.
    4. I do not understand the question. The MPPSET pin only controls the charging current such that the panel voltage does not drop below a certain value. The battery charger has no control over how much voltage is being supplied by the panel. It only helps maintain the output power of the panel.
    5. I do not understand completely understand the question. Additional capacitance may help with noise, but it may not treat the root cause of your noise issue. A good layout is very important in reducing the noise/EMI generated from the PCB.