LM5030 Softstart Threshold

Jeremy,
If you look at the block diagram on page 2 of the LM5030 datasheet, you can see that there is a nominal 1.4 V offset from COMP to CS, as well as a an attenuation of 0.33 nominal. This means that the COMP level has to reach at least 1.4 V before PWM will commence, at very small duty cycle. Tthereafter, for every 300 mV increase in COMP, there is a 100 mV increase in the peak current demand at the PWM compatarot, i.e. 100 mV increase in the peak current at the CS pin. The COMP to CS gain is listed in the datasheet electrical table, but unfortunately not the offset.
For the SS pin, there is a nominal 0.5 V offset between COMP & SS. This is not shown in the block diagram, but is listed in the electrical table.
At startup, as the SS pin level rises, the COMP pin is clamped to the same level, plus the 0.5 V offset. Thus once COMP reaches nominally 1.4 V, i.e. when SS is approx 0.9 V, this is level where the peak current demand level at the PWM comparator starts to rise above zero, and PWM activity starts.
This is close to the 1.05 V level you observed, the difference could be down to IC tolerances, or maybe that the levels have to rise slightly more so noticeable pulse-width drive pulses can be observed.
The shutdown threshold on the SS pin is relevant wrt putting the IC into a low power standby mode. As can be seen from above, the PWM activity will already stop when SS goes below about 0.9-1 V due to the functionality, but the IC will not be in low power mode. Bringing the SS pin below the lower shutdown threshold will then further drop the IC bias consumption.
I hope this helps to explain the block diagram and functionality a little better.
Thanks,Bernard

Bernard,

Thanks for the very thorough answer.  This makes perfect sense.

Jeremy