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How do I set BATLOWEN on the BQ27441-G1?

Dean Velasco
Intellectual 890 points
Other Parts Discussed in Thread: EV2400

I'm having some trouble setting the BATLOWEN bit.  I find that I get the expected default value of 0x25F8 for OpConfig when I read registers 0x3A and 0x3B.  When I try to set the BATLOWEN bit (bit 2) and read the results back though, the contents remain unchanged.

This is the sequence of operations that I'm using:

Write 0x00 to register 0x00   // Unseal the memory

Write 0x80 to register 0x01

Write 0x00 to register 0x00 again

Write 0x80 to register 0x01 again

Write 0xFC to register 0x3B

Write 0x20 to register 0x00   // Reseal the memory

Write 0x00 to register 0x01

  • 0
    TI__Mastermind 24870 points
    Hello Dean,

    Please refer to the TRM section on how to configure data memory.

    Do you have an EVM or EV2300/EV2400 to configure the gas gauge?

    Thanks,
    Kang Kang
  • 0 in reply to Kang Kang
    Intellectual 890 points
    I did consult the TRM, which is why I included the steps on sealing and unsealing the data memory. I think I might have misunderstood a step or two, though.

    And unfortunately, I don't have an EVM handy.
  • 0 in reply to Dean Velasco
    TI__Mastermind 24870 points
    Hello Dean,

    Yes, I understand the flow listed.

    You unsealed the gas gauge and sealed it again.

    However, to configure data memory you need to refer to Page 15 of the TRM.

    Thanks
  • 0 in reply to Kang Kang
    Intellectual 890 points
    I appreciate your response, but I still don't quite understand. I'm sure that this is my failing somehow, but that is why I'm asking here... because there's doubtlessly something that hasn't registered with me yet.

    Page 15 mentiones the PREV_MACWRITE, CHEM_ID, BAT_INSERT, BAT_REMOVE, SET_HIBERNATE, CLEAR_HIBERNATE, SET_CFGUPDATE, SHUTDOWN_ENABLE, and SHUTDOWN subcommands. Are you referring specifically to the SET_CFGUPDATE command? All I'm asking for is some specific advice to point me in the right direction, never having used this device before.
  • 0 in reply to Dean Velasco
    TI__Mastermind 24870 points
    Hello Dean,

    Please try the following commands to send.

    Send 0x13 to 0x00

    Send 0x00 to 0x61 (enables block data control) - this allows you to change Data Memory

    Send 0x52 to 0x3E

    Send 0x00 to 0x3F (This configures the address that your parameter is in)

    This is what the TRM outlines for changing the parameter of design capacity. Do you think you could try sending these commands in order to change design capacity?

    WR is for write. For example WR 0x61 0x00 means write 0x00 to register 0x61.

    RD is read. For example RD 0x60 Old_Csum means read old checksum from register 0x60.

    I hope this helps a bit, let me know if you have more questions.

    Thanks!
  • 0 in reply to Kang Kang
    Intellectual 890 points
    I've got some partial success. I found that the CFGUPMODE bit in Flags() (bit4, 0x06) is set after I send 0x0013 to 0x00.

    However, even after I execute the remaining instructions (WR 0x61 00, WR 0x3E 0x52, WR 0x3F 0x00, WR 0x3A 0xFC), I find that reading 0x3A still gives me 0xF8.
  • 0 in reply to Dean Velasco
    Intellectual 890 points
    This is what I discovered. If I read 0x3C/0x3D, I get 0x053C -- the expected default value. However, if I execute the sequence of operations that you described (and that are listed in the TRM), reading 0x4A and 0x4B gives me 0xB004. I can write to these locations, as the TRM describes, but this does not effect any change in the values returned by 0x3C and 0x3D.