UCC28711 Duty Cycle Calculation Error

Amruth,

Eqn. 12 in the datasheet calculates the IC Dmax capability. This is limited by the need to allow enough Flyback off-time to meet the Dmagcc constant of 0.425 (I.e. the output diode conduction duty cycle must be at least 42.5%, and it will be clamped at this min level in CC mode), and the need to allow 1 half period of the resonant ring to get to at least the first valley before commencing the next cycle.

For your application, we would need to know the Flyback resonant ring freq, which will depend on the value of magnetising inductance, and the total switch-node capacitance. This ring freq is typically about 500 kHz to 1.5 MHz. Assuming 1 Mhz, a hlaf-period is then 0.5 us.

So for a design target Fmax of 50 kHz, the period is 20 us. Take out 0.5 us for the resonant ring, and 8.5 us for Dmagcc (0.425 x 20 us), this means that the IC Dmax_limit capability in the design will be 11/20 = 55%. The power stage should be designed for an actual operating Dmax somewhat less than the IC Dmax_limit for margin/tolerances - once the IC duty cycle reaches this Dmax_limit, it can no longer regulate the output. As the Fmax target is increased, the Dmax will decrease, since the resonat ring portion will be a bigger % of the switching period.

Regarding TI-Design TIDA-00173, eqn 18 is calculating the power stage operating Dmax at min input voltage and max load. This can and should be less than the IC Dmax_limit capability. The operating Dmax will depend on the chosen transformer turns ratio, and the output voltage, i.e. the size of the secondary voltage that gets reflected to the primary. More primary reflected voltage => smaller Dmax.

I hope this helps to clarify things?

Thanks,

Bernard