LM5060 "EN" delay

Hi Jess,

It would be much quicker than the fault delay.

Table 1 on page 12 of the datasheet shows that when EN goes low, the TIMER is still low (it does not begin to charge). This means the timer would not be running. Also the block diagram on page 10 shows that the EN circuit goes through 2x OR blocks and then ties directly to the 2.2mA pull-down FET. Thus the delay would be the propagation delay of this signal, and then the time is takes for 2.2mA to pull-down the FET (this can be calculated depending on how many nC it takes to shutoff the FET).

Although we do not have a spec for it, my guess is it will very likely be <1us, and certainly may be <0.1us for the time it takes the LM5060 to respond and begin to pull-down the FET. Then it would depend on the size of the FET and its nC / gate capacitance.
 
Thanks,
Alex