This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC28950 unused terminal

Other Parts Discussed in Thread: UCC28950

If following terminals are unused, these terminals should be "pull-down"?

pin#8  DELEF
pin#13  ADELEF
pin#15  CS
pin#16  SYNC

Best Regards,

Hide

  • Hello Hide

    pin#8  DELEF - The only circumstance where this pin is 'not used' is if Synchronous Rectification is not used and the OUTE and OUTF outputs are not driving SR gates. The best option in this circumstance is to tie the DELEF pin to ground with a resistor within the allowed resistor range of 13 kΩ to 90 kΩ.

    pin#13  ADELEF - Tie ADELEF to GND is ok, then 'the delay is fixed, defined only by resistor REF from DELEF to GND' see the datasheet - page 16

    pin#15  CS - This pin provides a system level function in both Current and Voltage control modes. In current mode control the CS pin provides the current signal that the loop needs for control purposes. Connecting RSUM pin through resistor to VREF switches controller to the voltage mode control with the internal PWM ramp. However, the resistor value still provides CS signal compensation for cycle-by-cycle current limit. I would NOT recommend tying this pin to GND because the cycle-by-cycle current limiting function is too useful to defeat. Do let me know if you have a special reason for wanting to tie this pin to ground.


    pin#16  SYNC - leave open circuit if you are not synchronising multiple UCC28950 devices.

    Regards

    Colin Gillmor

  • Hello Colin, I have a similar question regarding NOT using the CS pin. I have no current sensing circuitry implemented so far and would like to be able to use this chip without needing to sense current. Currently I have a voltage divider consisting of a 10k and 422 resistor to provide 0.2V at the ADEL pin and have the CS pin tied to the ADEL pin. Is this acceptable or do you perhaps recommend some other method to bypass any current sensing?
  • Hello Ruben

    You should tie the CS, ADEL and ADELEF pins to 0V - this will defeat the functionality of these pins.

    Set the device into Voltage mode control (VMC)  - RSUM should be tied to VREF. RSUM provides slope compensation but in the absence of any current sensing RSUM won't have any effect. I'd suggest you use a 10k resistor. Operation in VMC requires that you add a DC blocking capacitor in series with the primary of the main transformer - otherwise the transformer will saturate due to inevitable small differences in the volt seconds applied to its primary.

    If you don't use the CS signal than you lose the following functions

    Current limiting and over current protection - in both VMC and PCM (Peak Current control Mode)

    DCM - at low currents the UCC28950 disables the Synchronous Rectifier outputs (OUTE and OUTF). This is done to improve efficiency.

    Burst mode operation at light loads - burst mode improves light load efficiency

    Cycle-by cycle current limiting - (in PCM)

    Adaptive delays - the CS signal is used to modulate the dead times - this allows you to achieve ZVS over a much wider operating range than otherwise.

    It is certainly possible to do what you suggest - certainly you could do it to 'get you going' while debugging a prototype for example - but do consider if the absence of any current sensing input to the controller is going to compromise your final design in other ways.

    Let me know how you get on


    Regards

    Coliln

  • Thank you for your reply Colin,

    This is definitely good to hear and I will implement the functionality in this way.

    Thank you for your clarification.

  • Hello Ruben
    I thought it would take only a few seconds to dig up some suitable reference but in fact it's not too easy to find a good explanation of why you need a DC blocking capacitor in a VMC full bridge -

    Have a look at the articles at powerelectronics.com/.../Feature2_0309.pdf and Fig 3 and associated text in powerelectronics.com/.../310PET07.pdf (this refers to gate drive transformers, but the volt-second imbalance issue is the same.

    The basic problem is that the h bridge transformer is ungapped - this means that it will saturate at a very low DC bias current in its primary - with catastrophic results. the bridge is driven symmetrically but in practice there will always be some small asymmetry in the volt-second product applied to the primary. This asymmetry will allow a dc bias current to develop. The function of the capacitor is to prevent this current. What happens is that any initial small imbalance will drive a nett current into the capacitor which will then charge to some voltage. What voltage does it charge to ? - it will charge up to the voltage which corrects the volt second imbalance in the drive. The cap voltage will add when the bridge is switched in one direction and subtract when it is switched in the other. The capacitor needs to be able to carry the RMS primary current, it should also be rated to withstand the full input voltage and its value should be large enough that the capacitor voltage does not change much due to the transformer primary current during a single switching cycle

    www.ti.com/.../slup132.pdf gives lots of useful information about magnetics in general - Section 2- 4 regarding flux walking may be of particular interest to you.

    There is a lot of good PSU design information in that TI PSU design seminar archive at www.ti.com/.../login.shtml

    Regards
    Colin