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LM5067 charges output caps when UVLO pulled low.

Thomas Ham14
Prodigy 110 points
Other Parts Discussed in Thread: LM5067

On the eval board I connected UVLO to VEE, flipped the power switch on and watched VOUT. Even though UVLO was pulled to VEE, the output capacitors slowly charge. I was expecting the output to remain at approximately 0V. The MOSFET gate is at around 12mV so it seems to be off. Any ideas why the eval board is not working as expected?

Thanks.

  • 0
    TI__Genius 12621 points
    Hi Thomas,

    I repeated your experiment and saw the same behavior in our lab. I'll ask our systems engineer for guidance when he returns next week.

    My guess is that it's leaking through OUT bias current or leakage through the MOSFET (this would be simple to test by removing the MOSFET and seeing if the leakage disappears and/or cutting the OUT pin trace to test).

    Thanks,
    Alex
  • 0 in reply to Alex Triano
    Prodigy 110 points
    Hi Alex,
    thanks for the quick action! I had already lifted the MOSFET and of course, the leakage stops. For now, I have placed a resistor across the bulk caps to bleed them but this seems kind of wasteful. I will be interested to here what your team ahs to say next week.

    Best Regards,
    Tom
  • 0 in reply to Thomas Ham14
    TI__Genius 12621 points
    Hi Thomas,

    Ultimately we cannot reduce leakage through the turned off MOSFET. The LM5067 EVM uses the SUM40N15 which has 1uA of leakage at room temp:
    www.vishay.com/.../72155.pdf

    (Page 2, "Idss").

    So even a 100k resistor should keep the voltage below 100mV.

    Thanks,
    Alex