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LMZ21700 drawing high power when Vin < Vout

Kuenrg
Intellectual 480 points
Other Parts Discussed in Thread: LMZ21700

Hello,

  I have a design using a LMZ21700 to buck voltage from 4.2V (from a battery) down to 3.6V.  The load is able to operate from 3.8V down to 3.1V.  The expectation was that below 3.6V the output would drop with the input and the load can measure the incoming voltage and sense when the battery voltage is getting too low.  

  The circuit works fine but once the battery voltage falls below 3.6V then it seems to draw 1mA quiescent current.  

  Am I missing something in the datasheet?  I have looked it over and I just expected the High Side Driver to simply go on but maybe I missed something.  Can the PWM mode it 100%?

  I am not using Power Good (It just goes out to a test point).

Thanks in advance!

  • 0
    TI__Mastermind 23845 points
    Hi,

    This could be that you are in the PWM mode instead of PSM (Power Saving Mode). Usually in the PWM mode you consume more power.
    When VIN is almost equal to VOUT, the duty cycle is close to the maximum duty cycle. In this case if you keep dropping VIN, the VOUT will also drop since you will be out of regulation due to max duty cycle limitation of the part. When this happens i believe that you are in PWM mode since the frequency will be fixed and not decreasing anymore.

    You can see the difference when you have a 4.2VIN and 3.6VOUT, when you reduce the load current, the frequency on the SW node should be decreasing since you are entering a PSM mode as you lower the load current

    Thanks
    -Arief
  • 0 in reply to Arief Hernadi
    Intellectual 480 points

    Thanks!

    So the load is quite variable - from <1mA to 200mA for short while.

    To clarify, in PSM does the algorithm allow the FET to turn on fully and just pass the voltage onto the load?

    In PWM mode does the algorithm allow the FET to turn on fully?

    (I am asking because these modes are based on inductor ripple current and, as far as I can tell, at Vin < Vout the FET should have an on time of 100% and therefore have low inductor ripple current.)

  • 0 in reply to Kuenrg
    Intellectual 480 points

    I just did a TINA Simulation of the circuit (LMZ21700 - 3.2V Vin, Rfbt = 1.07M, Rfbb = 300k) and I got 6.41uA on IIC.  Not very familiar with TINA at all but I think it's correct.

    LMZ21700_3.2Vin_3.6VTarget_Vout.TSC

  • 0 in reply to Kuenrg
    TI__Mastermind 23845 points
    Hi,

    I dont think the FET could be on 100% in either mode since they have to charge the internal bootstrap capacitor.
    Would you mind correlating the bench and the tina spice result on the SW node frequency?

    Thanks
    -Arief
  • 0 in reply to Arief Hernadi
    Intellectual 480 points
    Yes, I will scope the SW node. I'll let you know what the results are. I've continued to play with my TINA simulation and I think I'm still not doing something right there; I think my previous upload isn't valid.