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TPS62065 - EVM (SLVU364–March 2010) layout questions

Igal Kronshtein
Prodigy 120 points
Other Parts Discussed in Thread: TPS62085, TPS82085

Dear TI,

Few questions regarding the EVM layout:

(1) The PCB stack-up is not clear. Is layer 2 close to the Top layer?

(2) Why there is a GND opening under the DC-DC in Layer 1?

(3) Why GND to FB resistor is connected thru net to AGND pin? (and not thru GND plane)

Thanks,

Igal

  • 0
    TI__Guru**** 150950 points
    1. Yes, layer 2 is the next one under the top layer. Figure 15 should be labeled layer 3. It's a 4 layer board.

    2. I believe this is Figure 15, which is really the 3rd layer in the PCB. This simply provides a GND flood to tie all those vias together. It's not needed.

    3. It is recommended to route the FB divider directly back to the AGND pin to eliminate any noise impacts from affecting that critical signal.

    You might look at the TPS62085 or TPS82085 as higher power, newer converters.
  • 0 in reply to Chris Glaser
    Prodigy 120 points

    Hi Chris,

    Thanks for the answers.

    Regarding item 3 - it is not clear why AGND (to FB) is routed as a separated net in Bottom layer, while pin 3 is connected both to GND paddle and the GND via near this pin is connected to GND plane in Layer 2. Please advice?

    Thanks,

    Igal

  • 0 in reply to Igal Kronshtein
    TI__Guru**** 150950 points
    Layer 2 is AGND, so the vias can tie there with no issue. If that GND plane were connected to the input and output headers as well, I would not recommending connecting the GND vias to the plane.