BQ76920 OVRD_ALERT bit behavior questions

DAVID BROBST

I am having problems with the OVRD_ALERT bit in the in the SYS_STAT register. It is getting latched as a '1' and disabling the outputs (DGS_ON = 0). I can clear it and everything works OK. However, I am trying to understand why the OVRD_ALERT bit is getting latched as a '1'. I have the ALARM line tied to an input on a micro with a pull down resistor. Any help in figuring this out would be appreciated.

Dave Brobst

over 10 years ago

0 WM5295 over 10 years ago

TI__Guru 54715 points

If the part samples the bit as a high it will set OVRD_ALERT. Check for glitches from the MCU or crosstalk to any nearby signals. A heavier pull down or small capacitor may help, but both will increase current. The time constant on the signal should not be more than approximately 250 us to avoid having the part sense the signal as high after it has been cleared.

0 DAVID BROBST over 10 years ago in reply to WM5295

Intellectual 440 points

Thanks, I will try to induce a noise event on the the ALERT line to see if I can recreate this.

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BQ76920 OVRD_ALERT bit behavior questions