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TPS54625 Failure to start on transients

Stephen Hicks39
Prodigy 30 points
Other Parts Discussed in Thread: TPS54625

I am using a TPS54625 to power a 5V system.  This is a consumer electronics product.  When testing the product, I have noticed that an intermittent input power connection can cause the system to appear to have no voltage.  I've done some testing and found that a short transient of no power after a successful power-up is apparently triggering the under-voltage latch (UVLO) and causing the part to shut down.  Is there a solution to this (other than a crazy about of bulk capacitance on the input)?

 Here is what a typical startup with a little noise looks like.  The input voltage (yellow) is 13V roughly (minus a diode drop).  The output voltage (blue) is set for 5.2V.

Even with a little noise it is fine.  Also, it recovers fine if there is a large gap of no input voltage such as this:

Notice that it stops providing output, but when the voltage is again asserted, the system restarts. 

But short gaps in the input voltage -- in the case caused by connecting the unit to power with a clip lead and dragging the lead a bit causing an intermittent connection -- results in the system failing to product output after the input transient:

In this particular case, you can see there were two transients, but it happens regularly with a single transient in the same time range, 10-25ms or so.  Any thoughts on how to prevent this from happening?  The data sheet indicates that the UVLO function is non-latching, but this tends to make it look latching to me.

In the fail state, Vout is 0V, VREG5 is 5.47V and PGOOD is low.

  • 0
    Prodigy 30 points
    -- transients in the 5ms range, rather, cause the issue. Not 10-25ms.
  • 0
    TI__Genius 15780 points

    Hi Stephen,

    This device belongs in the Non Isolated DC/DC Forum.  I will go ahead and move this post there.

     

    Regards,

    Alek Kaknevicius

  • 0 in reply to Aleksandras_Kaknevicius
    TI__Guru**** 191445 points

    While the input voltage UVLO is non latching, the output voltage under voltage protection (UVP) is latching.  When the UVP is triggered due to the input voltage falling, the device is latched off.  If the input voltage falls below the UVLO threshold, the device will restart when the input voltages rises again.  If the input voltage does not fall low enough to trigger UVLO operation, the device is not shut down.  The output will remain latched off until power is cycled or the EN pin is toggled.

  • 0 in reply to JohnTucker
    Prodigy 30 points

    OK thanks for the quick response.  If I understand you correctly, if the voltage transient falls in-between the UVLO and the UVP, the device will latch off and I will have to toggle EN to restart.  I was considering using a larger capacitor on the SS pin to bridge any power connection transients that might occur.  Does this seem like a workable solution?

    Thanks,

    Steve

  • 0 in reply to Stephen Hicks39
    TI__Guru**** 191445 points
    Not exactly. The UVP detects the output voltage. The UVLO detects VREG, which is derived directly from the input voltage. If Vout falls below the UVP and Vin does NOT fall enough for the VREG5 to trigger the UVLO, then the device is on, but switching is latched off. A longer SS time may help as UVP does not enable until after 1.7x the SS time. It would probably be better do just not enable the device until your input is stable.