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Re: TPS65910A3A not generating +1.5V for DDR3 but +0.94V

Burt Hashizume33
Prodigy 170 points
Other Parts Discussed in Thread: TMDSICE3359, AM3352, TPS51200

I have a TPS65910A3A PMIC driving an Am3352 with a single x16 DDR3. Most of the voltages out of the PMIC are good except VDDIO. It should be +1.5V and it is only +0.94V. This occurs on multiple boards. I've connected the PMIC with the Am3352 almost identically to the TMDSSK3358 and TMDSICE3359 schematics.

VBAT and VBACKUP are +5.0V. Boot1 is connected to PMIC_VRTC, Boot0 is connected to ground. PMIC_VRTC is not connected to anything else. PWRHOLD is connected to +5.0V and PWRON is pulled up to +5.0V and connected to a push button. The RTC is not used so OSC32KIN is connected to ground and the OSC32 and CLK32 outputs are open. nRESPWRON goes straight to the Am3352 PWRONRSTn. The pcb has a ground pad under the PMIC and I believe the PMIC is soldered to the pcb pad. I have all the recommended capacitors (2.2uF, 4.7uF, 10uF) and inductors (2.2uH) that are in the reference designs.

VDDIO powers the Am3352 VDDS_DDR, the DDR3 VDD, and a TPS51200 VLDOIN. The TPS51200 provides DDR_VREF to the Am3352 and DDR3 and VTT to the DDR3 termination resistors.

VDD1 and VDD2 are both +1.10V. VDIG1, VDIG2, VAUX1, VPLL, VDAC, and VRTC are all +1.8V. VAUX2 and VAUX33 are +3.3V. BUT VMMC is +3.7V, which is another problem.

Any insight as to where the problem is would be appreciated. Any suggestions where to look?

Thanks.

Burt.

  • 0
    TI__Genius 10885 points

    Hi Burt,

    Thanks for the thorough post. You mentioned VDDIO, which is an input pin, could this be a typo and you are referring instead to the VIO/SWIO rail?

    If VIO is too low, can we confirm if the current limit has been increased in the VIO_REG ILMAX bits? By default this rail will be limited to 500mA and if for any reason this is not enough you could see the regulationd drop out..

    If the voltage is still low, can you remove the load and see if the PMIC rail pops back to 1.5V?

    You mentioned VMMC is 3.7, is this the input to the VDDIO rail?

     

     

  • 0 in reply to Richard Solarski
    Prodigy 170 points

    Hi Richard,

    You are correct, it is not the VDDIO pin but the VIO voltage at the VFBIO pin.

    I didn't think the 500mA current limit would be an issue but I will check that possibility.

    VMMC does NOT feed VDDIO, VAUX33 does. VMMC provides power to VDDSHV1, VDDSHV3, VDDSHV5. and VDDSHV6. It is not connected to anywhere else except capacitors.

    Thanks for the response.

    Burt.

  • 0 in reply to Burt Hashizume33
    Prodigy 170 points
    Hi Richard,

    I've removed the DDR3 termination resistors so the load on VIO should be lower. The voltage is still about +0.93V. The voltage is not entirely stable. It oscillates +/-150mV every 16 usec. The average around +0.93V. The period and pulse width of the signal on the SWIO pin varies, which causes the VFBIO signal to oscillate.

    Moreover, at power on, VIO does generate +1.5V but drops down to the oscillating +0.93V a fraction of a second later.

    Burt.
  • 0 in reply to Burt Hashizume33
    TI__Genius 10885 points

    Hi Burt,

    Do you still see the oscillations when you set DCDCCTRL_REG [1:0] = 00?

    Is the feedback line close enough to the switch node in the layout to be directly coupling?

  • 0 in reply to Richard Solarski
    Prodigy 170 points
    Hi Richard,

    It will take some time to put together software which can read and write the I2C registers.

    The VIO feedback signal, VFBIO, goes to the PMIC pin 16. The switch node is PMIC pin 14 so at the PMIC those two lines are close. But since they come from opposite ends of the inductor, the signal traces split apart as soon as they leave the pins.

    Any ideas why the VMMC voltage is +3.7V instead of +3.3V?

    Burt.
  • 0 in reply to Burt Hashizume33
    TI__Genius 10885 points
    Thanks Burt,

    As long as the lines aren't close and parallel to each other they should be fine. Does VFBIO run unsheilded along any other switchers/agressors?

    VMMC could be getting back-fed from one of the peripherals. Are any of the peripherals running off of higher domains than 3.3V?
  • 0 in reply to Richard Solarski
    Prodigy 170 points
    Hi Richard,

    Pin VFBIO is also the VDDS_DDR voltage "signal". This "signal" is only trace etch for about 75 mils before connecting to a VDDS_DDR partial power plane. This partial power plane connects to the Am3352, DDR3, and TPS51200. VDDS_DDR shares the power plane with VMMC and +1.0V FPGA voltage. I see anywhere from a 10mil to 25mil gap between the partial power planes.

    Burt.
  • 0 in reply to Burt Hashizume33
    Prodigy 170 points

    Hi,

    This problem is not resolved but I have a work around.

    Changing VIO_REG[7:6] from 00 to 01 had no effect on increasing VIO from +0.94V to +1.5V. Changing DCDCCTRL[1:0]  from 11 to 00 also had no effect.

    Through the Am3352 GPIO, I just wrote a 0 to the TPS51200 EN pin (DDR_VTT_EN) to disable the generation of the VTT termination voltage and that allowed VIO to be at +1.5V. This means I have no external VTT termination resistance on the DDR3. This should be OK since I only have one DDR3 but I still don't know why I can't get +1.5V otherwise.

    Burt.

  • 0 in reply to Burt Hashizume33
    TI__Genius 10885 points

    Hi Burt,

    This is good to hear that you found a workaround, are you able to measure the current from VIO when the VTT LDO was enabled/disabled? I'd be curious to see if the demand on the regulator exceeds the maximum current limit, and it might correlate to the 16µS pulses you mentioned earlier. Did you notice if the voltage changed at all when you set VIO_REG[7:6] to 01, and would it rise any if you set VIO_REG[7:6] to 10?

    From here I would focus on all the connections after the VTT regulator, if the current is large then there could be short or accidental misconnection, and if the current is well under the limit then we'll have to determine what could cause such a specific regulation voltage.