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CS pin waveform of UCC28950

HIRATA MITSUO
Intellectual 490 points
Other Parts Discussed in Thread: UCC28950

Hello


The waveform of before RC low pass filter of UCC28950 is different from after it in CS pin of the attached file 1[circuit and wave form].
Customer would like to understand its reason.
And UCC28950 will have timing behaivor of the attached file 2 [CS pin timing chart].

Question1)
Is this timing chart correct?

Question2)
If Q1 is correct, please tell me relationship between CS signal and output control signal?

(Output control signal only depends on CS signal? or perhaps it has relationship with ramp?)

Question3)
When is ADSEL loaded and when are T_ABSET and T_CDSET decided in CS pin of this timing chart?

7624.UCC28950 Schematic and Waveform_pptx.pdf

UCC28950 CS timing.xlsx

  • 0
    TI__Mastermind 25570 points

    Hello Mitsuo-san

    The 10k resistor and 100pF capacitor (R310 and C251) give a pole at about 150kHz. The function is to filter out high frequency spikes, especially the 'leading edge' spike that happens when the power MOSFET switches turn on. You can see this spike on the V_R201 waveform. This is about 30ns wide (approximately) The purpose of the RC filter is to prevent this spike from tripping the comparator on the controller and terminating the switching cycle early. The comparators are the PWM COMP or Cycle-by-Cycle comparators in the device block diagram.

    The V_r201 waveform on the positive going switching cycle (C_T202_7-12) is different to that of the negative going cycle - I suspect that this is a measurement artifact because the filtered signal at Vcs is the same for the two cycles. One other thing to look at is that the leading edge of the positive going C_T202_7-12 waveform is faster than that of the leading edge of the negative going waveform.This might be due to some asymmetry in the gate drive systems that I can't see on the partial schematic you sent.

    Overall, the VCS signals look reasonable.

    The timing diagrams for OUTA, OUTD and r_201 in the excel file are correct. If the file below is not readable then please send me your email address and I will email it to you.  The CS signals will follow the V_r201 signals - The ADEL and ADELEF levels are evaluated at the time the PWM_COMP comparator trips.

    Please let me know if you need any further information

    Regards

    ColinCopy of UCC28950 CS timing.xlsx

  • 0 in reply to Colin Gillmor
    Intellectual 490 points

    Hello Colin-san

    Thank you for your respectable advice.

    I will answer to customer with your advice.

    If I receive another question from customer, I will ask for your advice.

    Thank you.

    Best regards,

    Mitsuo Hirata