LM5067 mosfet selection

Hi Teena,

For quickest support, can you attach the tool you already began filling out? This will help us check the design and discuss specific cells/parameters which can be tweaked.

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For hot swap design, the worst case condition is if there is a short circuit on the output and then the hot swap is turned on (turning on the MOSFET with a short present on the output). This puts the MOSFET in its linear region, where it has a high Vds voltage and current at the same time (high power dissipation). The LM5067 offers power limiting to help protect the MOSFET by limiting its power dissipation. Without power limiting, the MOSFET would simply burn (due to the >25A current limit) and the input would be end up permanently shorted to the output.

So that derated SOA/Plim checks that worst-case condition to determine if the MOSFET would survive at maximum current, maximum ambient temperature, into a short circuit. For explanations on the calculations used, check out www.ti.com/hotswap --> "Technical Documents" --> "Robust Hot Swap Design".

We also have a brand new video tutorial series to guide through each step of the hot swap calculator tools. Check out www.ti.com/hotswap --> "Support & Community".

The MOSFET you used looks pretty good (low Rds-on, high SOA) and may be sufficient for this design (will need to see the tools which shows all of your parameters such as total output capacitance and input voltage range). TI does offer the CSD19536KTT which is
similar but has a bit stronger SOA performance. For example at 70V Vds, the CSD19536KTT can take 9A for 1ms pulse duration, whereas the IPB020NE7N3 can take about 6.5A. This is almost 50% more headroom.

Thanks!
Alex

Hi Alex,

I have attached the tool that we have filled.

In the tool ,on what parameters does P(lim,min) depends and what is its  importance?LM5067_Design_Calculator_REV_C.xlsx

Hi Teena,

You can check out the brief description in section 3.1.2.3 of this app note which can also be found at ti.com/hotswap --> "Technical Documents":

To summarize, the IC has systematic offset which is not taken into account in the original power limiting equation. As a result, if the system offset varies too high or two low, then power limiting accuracy can change considerably.

Consider if you turned on into a short circuit and tried to set a 6W power limit with 60V input and a 1.5mohm sense resistor. This means limiting current to 0.1A across 1.5mohm, which is 0.15mV of voltage sense signal. The amplifier is not accurate at such a low value, and system offset of 2mV would greatly overshadow this value.

So fundamentally there is a minimum power limit which should be used. Originally, we did not have any test data so we conservatively suggested to keep power limit setting above 5mV.

However, we have done some test data more recently and noticed the systematic offset appears to be quite small for the LM5067 in particular. So using a lower power limit is probably ok. See this data:

Since the system offset is so small and the old equation and new equation are very similar, we do not currently plan to update the datasheet due to this data (though the equation will be updated in its next rev).

However, based on this data we can update the tool and lower this minimum power limit to at least 2-3mV.

As for this design, we see that it would likely fail a short circuit test at elevated temperatures. Some ways to improve would be:

1. Switch to a stronger SOA MOSFET such as the CSD19536KTT. Since this design is 60V max Vin, the 60V Vds line is the most critical within the SOA curve.As you entered correctly, the IPB020NE7N3G FET shows 2A for 10ms pulse. The CSD19536KTT shows 3.5A under the same conditions, which is 75% more robust. Also note that the TI FET team has a dedicated SOA destructive test machine to characterize this SOA curve based on actual failure points. So this MOSFET's datasheet values for the SOA have already been derated (usually by ~30% below the failure point for most new NexFET datasheets). So you should be able to operate very close (or at) this SOA curve point and be safe.

2. Consider using 2x MOSFETs in the design, or else good heatsinking to lower the steady state MOSFET temperature. Note that the MOSFET's max Rds-on may be 2mohm at 25C, but it will increase at elevated temperatures. So if operating up at 75C ambient, the MOSFET may go up to 3mohm at least and have a junction temp of 120C or higher depending on heatsinking.

3. If suitable for your system, decreasing the load capacitance on the hot swap output will mean less energy through the FET during startup. This allows you to decrease the timer capacitor.

4. Consider splitting the loads into 2x hot swap designs, each with a single LM5067 controller and single MOSFET. This would reduce the stress of each hot swap design.

That is about all the simple tweaks we can recommend but overall, a 60V 25A design with short circuit protection and 1000uF output capacitance is difficult to do. Splitting the loads and doing 2x 15A designs for example would be much easier and more robust.

Edit: Correction, it is difficult to design with these specs for a negative (low side), -60V solution. For a +60V solution with the LM5069, this design would be easier.

Thanks!

Alex