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LM5050 In-board MOS Short to Ground Problem

Winston Chang
Prodigy 100 points
Other Parts Discussed in Thread: LM5050-2

I am damaging the OR-ing FET controller (LM5050-2) almost every time I perform an inboard MOS short.  We have a local 2.2uF ceramic capacitor and a 3A SMA Schottky diode at the input (pin 4) and no ceramic at the output (to minimize disturbance during hot-install).  The application is a 200V to +28Vdc, 500W converter on a 3.5" x 3.5" area PCB.  The OR-ing is selected for low power dissipation, despite the recommendations of TI's application notes.  The PCB is the heatsink for the OR-ing FET and the PCB receives no air flow.  The only options are to reduce loss or to use the method of conduction to case which is not desirable in this case.  We are testing in a N + 1=3 configuration.  I was wondering if anyone else has encountered similar failures and what was done to alleviate the problem. 


The output stage is as follow:

Since the OR-ing controller regulates the D-S of the MOS to 27mV, I am not presently getting the full benefit of the low Rdson part.  The recommended Vds per TI's application note is 20-100mV and I am at 18mV.  One possibility is to back off  a bit on the MOS and to use slightly higher Rdson parts.  I am probably unable to increase Rdson more than a factor of three and despite the fact we should expect earlier detection of fault current (27mV/Rdson), the increased Rdson part does not change the short circuit fault current significantly.  Hopefully I will be pleasantly surprised.

Any insights, comments, suggestions, recommendations are appreciated.  Thank you!

Regards,

Winston

  • 0
    TI__Expert 5940 points

    Hi Winston,

    Lets begin with the 1st part of your input now and discuss the 2nd afterward.  Is only the controller damaged or is the FET also?  What FET is used?  Have you tried to use a TVS on the output to guard against Vout high going spikes like fig 22 of the DS show?  Output parasitic inductance will cause this when the FET is turned off rapidly from the resulting di/dt (like it is supposed to do to limit reverse current).  Some designs can get by without major protection on the output if the inductance is very low, relying on the voltage rating of the LM5050 or an output cap alone to absorb some of this.  Your design has no output cap.   See fig 24 in the DS that shows both the Schottky on the input and the TVS on the output.  D2 = SMBJ60A-13-F, 60v, 600W TVS. 

    Brian

  • 0 in reply to Brian Daugherty
    Prodigy 100 points
    Hi Brian,

    Only the LM5050 is damaged.

    Per the schematic excerpt, the MOS is a BSC010N04LS. There is no output capacitor to minimize disturbance during the hot-install event.

    Since we encountered the first number of failures w/o output capacitor, we added a local 1uF ceramic at the output pin (pin 6) for testing only. It did not help.

    Perhaps a true TVS may be better for the application but the plan was to use the MOS's avalanche voltage rating as the TVS (approx 40V@25C, 1mA per DS). The rationale was that the parasitic diode was far more robust than any 5W SS, 600Wpk TVS could be, although it is rarely characterized to the extent needed. I will revisit this aspect to make sure 100V is not exceeded.

    I have managed to improve the robustness of the circuit a lot by adding a small series resistor (1/2 ohm) between the source of the OR-ing MOS and pin 4 (IN pin) of the LM5050. The bypass capacitor (from pin 4 to pin 2) had to be reduced to 22nF to keep response time sufficiently fast. It is not clear to me what in the LM5050 requires me to reduce the capacitance so much. So far we managed to sustain 60 short circuit events w/o failure but the need for this method of solution is a bit disturbing.

    Winston
  • 0 in reply to Winston Chang
    Prodigy 100 points
    Hello Brian,

    Let me follow up and provide an update of our testing results.

    By using a variation of the solution described in my last mail, we were able to achieve improved performance without degradation in LM5050-2 robustness (>60 SC events). Based on our testing it appears that the architecture of the device is probably designed only for low power/current applications where the fault current and system inductance are "relatively" low. In our application, the fault current can exceed 450A peak. Under that scenario there is no way a 1A SMA or a 3A SMA Schottky (per DS) can clamp the voltage at pin 4 with respect to pin 2 to the absolute maximum rating of 0.3V (per DS). It is this pin we are damaging.

    We revisited whether there is any possibility transients on the output side is damaging the device. For initial test, we added a 1uF, ceramic from pin 6 to pin 2. The peak voltage ring was 42V.

    We then removed the 1uF capacitor to test whether it was viable to use the avalanche parasitic diode within the MOS as a TVS. It worked very well. Not only did the LM5050-2 survive multiple events, the clamp voltage @25C was 73V peak, < 100V device rating.

    Winston