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TPS650830 DDRID pin

Antony Lin
Genius 13480 points

Hi,

If we do not care about the impact to the system, can we dynamically change DDR voltage from 1.2V to 1.35V (vice versa) by controlling DDRID pin?  Do we need to turn it off before we change DDRID level for such control?

Thanks!

Antony

  • 0
    TI__Genius 16870 points

    Antony,

    Since the controller will not force PWM when the voltage is dropped from 1.35V to 1.2V it is recommended to mask the VR4 fault and force PWM during transition. Then unmask the fault after stead-state.

  • 0 in reply to Michael Green
    TI__Genius 13480 points
    Hi Mike,

    Can you elaborate more about "force PWM during transition"? Do you mean to configure it as force PWM mode during DDRID level change or we need to turn off VR4 and change DDRID level, and in the end turn on VR4 again?

    THanks!

    Antony
  • 0 in reply to Antony Lin
    TI__Genius 16870 points
    Well there are 2 ways of accomplishing the same task: A and B.

    A) 1. keep VR4 on the entire time
    2. set fault mask on VR4
    3. force PWM mode
    4. change DDRID pin
    5. switch to PFM (auto) mode
    6. un mask the VR4 fault
    7. Voltage transition is complete

    B) 1. turn VR4 off for transition
    2. set VR4 discharge resistor to 100 ohm using V12UDISHCHG bits
    3. disable VR4
    4. change DDRID pin
    5. enable VR4
  • 0 in reply to Michael Green
    TI__Genius 13480 points
    Hi Michael,

    For case A as you propose, do we need to insert any delay between the steps?
    Do we have the slew rate from 1.2V to 1.35V and from 1.35V to 1.2V?
    Does it spend 16 cycles (either 500KHz 800KHz) from "Force PWM" to "Auto" and from "Auto" to "Force PWM"?

    THanks!

    Antony
  • 0 in reply to Antony Lin
    TI__Genius 13480 points

    Hi Mike,

    Do you have any update regarding this?  Additionally, do we need to do anythig (e.g. register configuration)  regarding VTTLDO for such scenario?

    Thanks!

    Antony

  • 0 in reply to Antony Lin
    TI__Genius 16870 points
    There is really not any delays required as the transition in forced PWM will be fast in the us range. VTTLDO will not be adversely affected because it just tracks the VDDQ to 1/2 which it will do and you can see the Vout changes accordingly for a VR4 shift. The VTT fault is already masked due to another reason.