Dear, All
I ask about UVLO of LM3481.
Please tell me time until DR output will be Off after UVLO pin reaches the Ramping Down voltage.
I'd like to know time of typ. and max.
When detecting OV and UVLO, the customer would like to stop LM3481 using UVLO pin.
OV and UVLO detect it by the outside circuit.
Thanks, Masami M.
Hi Masami,
I couldn't find any timing diagrams showing this so quickly tried this on the bench, I used a Ti board configured as a boost, the external FET was VISHAY SI4368DY, not sure what your customer is using.
For this set-up it looks like when UVLO is active the DR pin goes low in ~300us, DR voltage in this case is 4V before UVLO is triggered. Please see 2 plots below, this gives an indication of the DR pin in Ti EVM when UVLO is triggered, second scope shot is Zoom of the first showing timing, 100us/DIV.
1 device tested only.
Green trace is VOUT
Yellow trace is DR pin
Pink is VIN
I did bench testing as the data was not available in datasheet . The typical value of the time elapsed between UVLO trigger and Drive pin output is 200nS . I did this testing on TI Evaluation board with 3-11V input and 12V@2A output (took data at various Vin and output current).
Yellow is UVLO in and Red is Drive output
