UCC28700 regulation issue

Hi Eitan,
there may be many reasons for the voltage regulation. i would give you some suggestions.
1. check the average working frequency at full load. you may monitor the DRV signal and calcualted the frequency by measuing the duration of 20 DRV pulses. if the wokring frequency near 120k, it would have problems.
2. check the IOCC point. by setting the ELOAD on CV mode. be sure it can sustain more than 2A.
3. if you are still have some uncertain, please share the schematic/bom/ transformer spec to me.
4. when you change RLC from 4.76k to 1k, it makes the real ipk of MOSFET higher.
BrKening

Hi Eitan,
I would agree that the frequency limitation and IOCC point are not problems.
Your descirption about VS cap indicated the voltage sampling problem.
1. could you capture the scopes of Aux winding at full load with enough detail on the screens.
2. Could you share the pcb layout to me?
3. please also try to decrease RLC to zero. it will effect the IOCC point, however we may know whether there is noise on CS detection.
Br

Kening,

I decreased the RLC to 0, now the drop is from 5.3 to 4.8 at full load - a small improvement related to where I used 1K.  

I attached the Aux winding voltage sampling and also how it looks like on the VS pin.  I also attached a PCB layout - the PCB contains many other elements, to simplify I removed other non relevant elements. It may be noticed that R16 is a little bit far away from the regulator, however I tried to remove it and place it very close to the VS pin with a wire directly to the AUX transformer pin but nothing noticeable changed.

Thanks,

Eitan

7750.layout.pdf

VS pin.pdfaux_full load1.pdf

Kenning,

I attached the AUX directly and also on the VS pin at full load. I provided a chart of the PCB assembly showing related components as the layout itself has a lot of other parts so it may be confusing. Youy may notice that R16 is a little bit far away, I tried to put it directly on the VS pin and wire it to the aux winding but noting noticeably changed.

Changing RLC to 0 made some improvement over a 1K value, now the voltage drops to 4.8V. 

Best Regards,

Eitan

4520.layout.pdf6685.aux_full load1.pdf0410.VS pin.pdf

Hi Eitan,

First, please try to modify the snubber circuits. remove TVS D7, Change c21 TO 680p. decrease R13 to about 300 ohm. Please also capture the Aux winding scopes.

Second, the assemble drawing is not enough for the layout review. would you provide the layout file

Kening,

I tried to modify the snubber as you suggested, it changed nothing related to the regulation, however the situation become worth as I was starting to get a lot of noise on the output.

I attached here a snapshots of the PCB layers. Note that there are many other not related components on this PCB. Also note that on the layout R16 is actually 2 resistors in series (R16+R22), similar are R23 = R23+R24.

I also attached a cupture of Aux winding scopes (I hope this is what you looked for).

Thanks,

Eitanaux_full load2.pdflayout1.pdf 

Kening,

You did not answered my last post. Is it because you have no solution / suggestion? I consulted with a friend about that and he claimed that with this design it is expected that the regulation will be bad - is this correct?

Thanks,

Eitan

Hi Eitan,

It is hard to read the layout. What pcb software are you using? i can read altium, Pads, and Orcad files.

However , i am sure that the regulation supposed to be better than yours. there must be something worong with your designs.

TI has many reference design in the website with the regulation data such as PMP8477, PMP4351, PMP8286 etc..

The root cuase could be hided.

You are measing the output voltage at board end(Output cap), right? if with long wire, the voltage drop on the wire could be large.

You cannot probe on VS pin, instead it you should probe the AUX winding voltage. In some cases, the misdetection of Voltage could case a bad regulation.

Another thing, please make sure the VDD is always higher than VDD uvlo point at full load.

 

Br