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Freescale iMX6 for power on sequence with the requirement TPS65911x

Wang Kris
Intellectual 270 points

Freescale for power on sequence with the requirement seems with TPS65911x different.

Check on Freescale document as power timing instructions,

VSNVS_IN the first to start, then VDD_ARM_IN, VDD_SOC_IN, then the other power, and finally start the system POR_B.

ARM_IN / SOC_IN should be better than the other I / O to be early .

  • 0
    TI__Genius 10885 points

    Hi Kris,
    For the TPS659114, 3.0V and 3.3V rails are active before the 1.35V core rail, which should satisfy the documented requirements of SNVS before ARM and SOC for many of the i.MX6 processors. SNVS and HIGH_IN can often be tied together and even if both are supplied by the 3.3V rail the sequence would still satisfy the criteria. NRESPWRON should satisfy the POR_B if the internal functionality is not desired. Is there concern specifically with the I/Os after the core?


    For all designs, special care on the system level should be practiced to minimize any leakage paths that could occur from connected peripherals, and I/Os on the processor should not be externally driven when the associated NVCC_xx pins are not powered. A particular processor may not have some specific requirements, but considerations such as these are often application specific and should be taken into account depending on an individual design's requirements.


    Can you provide documentation that highlights your specific concerns here?