TPS54240 Burnt issue - mold compound crack

I think I answered this already...Since the VIN max is 39.5 V, most likely you have over voltage transients above the abs max voltage. Do you hot plug the input supply? Can I see the schematic and PCB layout?

Dear John,

Customer's application system with SMPS output 38~39.5V (Max) input to TPS54240. 

Customer had checked the transient during power ON and OFF (with SMPS bulk cap fully discharged) and no spike voltage is observed.

Please check the operational waveform as attached file. Actual operation condition, the transient Vin voltage is  0(off) ->14V (standby) ->38V(On) ->14V (standby)

The schematic, layout & BOM also attached in the file.

Application study report.docx

TPS54240 is used in 2 locations:

i) IC1002 :  Vin = 38V, Vout =16V, Iout max = 0.5A 

 ii) IC1003 : Vin = 38V, Vout =5.9V, Iout max = 2A

Both locations have IC failure symptom happens. However, the failure rate at location IC1002 is  higher.

Findings so far:

1) The phase / gain margin based on the components setting at Compensation pin(8) – The phase margin is 54.93 degree while gain margin is -14.47dB.

2) Also checked the temp rise data provided by customer, it seems the temperature margin is big.

3) Using general E-cap (C1021 – capxon GS series) for input capacitor

4) The inductor IL (100uH-0.7A, 33uH-1.7A)  rating is near to the operation current considering the peak current.(0.5A/2A).

5) Based on the failure samples(from last year till now), most of the defect samples has the mold compound cracked near pin 2 and 3. 

 

Questions:

1) Should Low ESR capacitor used for input capacitor?

2) Is the inductor current rating enough?

3) The voltage max rating for pin3 is low(5V) . Will damage of pin 3 (EN) lead to the failure symptom as customer encountered?

Hope you can review and suggest possible cause and improvement idea.

Thanks.

Best regards,

Chin

1) yes the input capacitor should be low ESR ceramic, X5R or better, It should be coupled to the IC Vin and GND pins as close as possible. It is ok to have additional bulk capacitance but you need a ceramic decoupling cap, about 4.7 uF minimum (or 2 x 2.2 uF).

2) I usually design with more current rating. It depends on you application though. If you can insure there are no over current conditions, then you can use a current rating suitable for your load only. If you expect over current or faults, then you need to rate accordingly. One good thing is most modern inductors have soft saturation curves. Even if you are well above the saturation current, the inductance does not decrease too fast.

3) yes you want to be careful about over voltage on the EN pin. It is ok to have the voltage higher so long as the EN source is high impedance. The EN current should not be allowed higher than 100 uA.

My other comments:

In general the layout looks ok. The input capacitor could definitely be moved closer to the IC and 4.7 uF ceramic should be added.

The output capacitances are rather small especially IC1002. I typically do not design with less than 2 x 22uF on the output.

You need to take a close look at EN. The schematic does not show how it is controlled, but overvoltage could be an issue.

It looks like you may have a sync clock. Check the timing of it.

Dear John,

Thanks for your valuable advice.

1) For the input ceramic capacitor (C1031), I will suggest customer to increase the value. How about the location and GND pattern? Shall it be moved to be parallel with C1021(E-cap) and sharing the same ground point? 

2) Since the IC has thermal shutdown protection and over-current protection, could I say that the failure most probably due to over voltage that lead to degradation of mold compound?

3) For the EN pin, customer controls EN from SoC, means the anode of the diode D1008 is connected to SoC for controlling (3.3V). Would the damage of this pin leads to the failure as my customer faced?

4) For the clock, customer does not use external clock. The resistor setting is 220k (fsw about 536kHz). There is other switch to control on/off connection for 1.8M resistor to change the fsw for AM beat proof function. Any problem?

5) Any possibility for back flow current until damage the IC?

5) Regarding the failure symptom encountered by customer, is there any way we can simulate the situation such as applying ESD?

Few defect samples had been analysed by TI

#1: Open pin: pin 2  ; Short pins: pin 1, 3, 4, 8, 9, 10
#2: short pins: pin 3, 9

#3 : Open pin: pin 2

#4 : Open pin: pin 2 ; Short pins: pin 1, 7, 8, 9, 10 

Seems like pin 2 opens and pin 3 & pin 10 shorted to GND are having high occurrence. Any hints or inference that you able to get from the analysis? 

Thanks.

Best regards,

Chin

Usually when there are multiple pins shorted, that means metalization flash has occurred. Typical scenario is over voltage causes high side FET to short. Now high current occurs and metal layers may melt, shorting other pins.

Pin 2 open means bond wires have most likely fused.

Pin 3 short may indicate some issue with EN, but could be random shorting from above.

For the ceramic input capacitor, you should place it closer to the IC than the AL electrolytic.

Back current would have to come from Vout being pulled above Vin so the body diode conducts.

It may possibly be ESD damage, I suppose you could test a board for susceptibility.

That clock change does not vary the frequency much, but who knows what happens during transient switching between them. RT pin is extremely sensitive. It is possible that switching frequencies is causing stress, especially if the Fsw dips very low during transition.

It is always difficult to capture these type failures. They are almost always caused by external conditions or layout, not faults with the IC.

Dear John,

Thanks for your further explanation.

With your information, I will discuss with customer how to proceed to study and resolve this problem.

Will need your advice again if we got new findings.

Thanks.

Best regards,

Chin