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TPS65910 I2C errata

Takahiro Ogo
Genius 5940 points
Other Parts Discussed in Thread: TPS65910

Hi,
I'd like know the detail of  TPS65910 I2C errata.

www.tij.co.jp/.../swcz010a.pdf
1 Glitch on SDA-SCL not managed correctly by the I 2C IP 

(1) I understood that TPS65910 I2C's function does not support "repeated start condition". Is this correct?

(2)The errata said that "This can cause the first real access after such a glitch to be corrupted".
 Even if (1) is correct, I can't understand why the glitch occurs. what is this glitch?


Because I do not know is this glitch, I do not understand the contents of the Description/Workaround.
Please let me know that.

Best Regards,
Taka

  • 0
    TI__Genius 10885 points
    Hi Taka,

    1) Incorrect, the TPS65910 does support standard repeated start conditions.

    2) The PMIC could interpret a sufficiently timed glitch as a start event, which could interfere with the recognition of an intentional start event. This could be caused by anything on the i2c bus.
  • 0 in reply to Richard Solarski
    Genius 5940 points

    Hi 

    Thank you for you kind support.
    Please let me ask some additional question about TPS65910 I2C errata.

    1)
    if there are no glitch on SDA/SCL, this errata is not affected.
    if there are any glitch on SDA/SCL, TPS65910 will recognize a wrong start event.
    Is this correct?


    2)
    TPS65910 doesn't support two consecutive Start condition. 
    So SCL line need toggle 2 times when TPS65910 recognize a wrong start events
    Because of that, Workaround is "Repeat I2C Access"(to re-toggle SCL).
    Is this correct?


    Best Regards,
    Taka

  • 0 in reply to Takahiro Ogo
    TI__Genius 10885 points

    1) Very close -  the glitch would have to fit the criteria of a start event (large enough voltage swing and properly timed) to be capable of tricking the TPS65910 into recognizing it as a legitimate start event.

    2) Correct.

  • 0 in reply to Richard Solarski
    Genius 5940 points
    Hi Richard-san

    Thank you for your kind support​.  I begin to understand ​this better.
    Please let me ask some additional question.
    1) I checked I2C bus specification.
    http://www.nxp.com/documents/user_manual/UM10204.pdf
    As the I2C bus specification, I2C device is required a input filter on SCL/SDA for HS mode.
    The Input filters suppress noise spikes of less than 50ns. (tsp)
    This "spike" corresponds to the glitch of errata?


    2)Finally, how much glitch ​on SCL/SDA ​does occur this I2C errata problem? (how voltage and time)
    Do you have any test data or wave scope?

    Best Regards,
    Taka

     

  • 0 in reply to Takahiro Ogo
    Genius 5940 points
    Hi Richard-san

    It would help if you taught about my question.
    My customer is waiting for your update.
    Thank you in advance for your cooperation.

    Best Regards,
    Taka
  • 0 in reply to Takahiro Ogo
    TI__Genius 10885 points

    Taka-San,

    Apologies for my delayed response, as I have yet to locate any relevant documentation over these specifics of the errata, and would have to re-create these conditions on an EVM. If your customer has a specific concern they can actually test their existing code on an EVM from our store:

    www.ti.com/.../TPS65910A3EVM-583

    They can wire into the i2c lines and test the robustness for their specific application. I would encourage them to post their findings on these forums, as it would help with developing more thorough documentation of this errata. How open would your customers be to evaluating an EVM?