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UCC28950 CS pin

Other Parts Discussed in Thread: UCC28950

Hi,

My customer is evaluating the UCC28950 and they have questions about it.

Please refer the following xls file mentioned waveforms of CS pin and a circuit.

UCC28950 CS-pin.xlsx

The voltage drop is occurred when the peak of detected current.

The voltage drop is raised when the resistor of RC filter is larger,

so my customer thinks that CS pin draws the current when the peak of detected current.

What reason is this voltage dropout ?

The setting of IC is following;

  - Control mode: Voltage mode

  - Master/Slave setting: Slave

If there is lack of information, please let me know.

Thanks and Regards,

Kuramochi

  • Hello Kuramochi-san

    I have not seen this difference in voltages at the CS pin that you show so I'll have to do some further work here to see if I can observe it here.
    Quantitatively, the difference seems to be about 1.7V in 1kOhm (= 1.7mA) and 700mV in 150 Ohm (= 4.6mA).

    Is the schematic you included complete ? - I wonder if there are any other components connected at the CS, ADEL or ADELEF pins or connected in parallel with the Raef and Ra resistors. For diagnostic purposes I suggest that the customer temporarily disable the adaptive delay feature to see if this current difference remains. Disabling ADEL and ADELEF is simply a matter of connecting ADEL and ADELEF pins to GND. The timing delays are then set by the DELAB, DELCD and DELEF resistors .

    I'll re-post once I have further information.

    Regards
    Colin
  • Colin-san,

    Thank you for your response.
    I send the completed schematic by e-mail, and I ask my customer to disable the adaptive delay.

    Thanks and Regards,
    Kuramochi
  • Hello Kuramochi-san

    There is an active ~200 Ohm pull down on the CS pin that is enabled during the 'primary off' time. That means that the pull down is activated when the PWM comparator trips and terminates the present switching cycle. An active pull down like this eliminates the (approx 200ns) propagation delays between the comparator trip and the output of the current transformer falling and allows us to reset the comparator for the next cycle sooner. This is the reason for the differences your customer has observed between the CS signal before and after the RC filter. these differences are normal.

    Regards
    Colin

  • Colin-san,

    Thank you for your response.

    About "an active ~200 Ohm pull down" are these R151/2/3 and R193?

    Best Regards,
    Kuramochi
  • Hello Kuramochi-san
    The active pull down is an internal circuit in the UCC28950 - I don't recognise the reference designators you mention above -
    Regards
    Colin
  • Hi Colin-san,

    I received the additional question from my customer.

    These are following;

    1. Could you show me the timing-chart when the pull down is activated?

       It seems that the pulldown is activated before OUTC/D turns off as the attached waveform.

    2. Is the current value that used the control and the protection the peak value(before the pull down active) ?

      If it is, does it mean that the my customer should consider it when they set the dead time and the over current protection ?

    Please let me know if there is any lack of information.

    Thanks and Regards,

  • Hello Kuramochi

    I don't have a timing diagram for this operation but it can be simply explained.

    When the signal at the CS pin reaches the control setpoint the PWM COMP comparator trips. This event activates the CS pin pull-down and also changes the state of the OUTX  outputs which then turns the switches at the transformer primary off. The propagation delay from the output of the PWM COMP to the CS pin pulldown is much shorter than that from the PWM COMP output to the switches at the transformer.  You correctly identify the 'current value used for control and protection' in the screenshot above. The 200ns time delay from the CS signal pull down to the transformer switch off is reasonable and would be made up of some propagation delays within the UCC28950 plus propagation delays through the FET drivers plus turn-off delays in the MOSFETs themselves.

    The choice of dead time setting must take account the external propagation delays and the switching characteristics of the devices used. What is important is that the designer provides enough dead time for the power stage to achieve ZVS. The dead time calculations in the Data Sheet can take account only the characteristics of the UCC28950 - TI has no control over external factors such as propagation delays.

    The over current protection will operate in the normal way of course but the actual current in the power circuit will be larger than the current protection threshold by a small amount - whatever the current increase is during the propagation delay time (200ns) in this case

    Regards

    Colin

  • Colin-san

    Thank you for your answer.
    I'm going to tell the my customer.

    Best Regards,
    Kuramochi